Method of forming an interlayer dielectric material having...

Details Method of forming an interlayer dielectric material having... Method of forming an interlayer dielectric material having...

2008-05-28

2011-11-01

Ahmed, Shamim (Department: 1713)

Etching a substrate: processes

Nongaseous phase etching of substrate

Using film of etchant between a stationary surface and a...

C216S084000, C216S087000, C216S089000, C438S692000, C438S693000

Reexamination Certificate

active

08048330

ABSTRACT:
By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during the planarization of the interlayer dielectric layer stack prior to the formation of contact elements.

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Translation of Official Communication from German Patent Application No. 10 2007 063 271.3 dated Jul. 17, 2008.

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