Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2002-04-08
2003-09-16
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S428000
Reexamination Certificate
active
06620703
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor device, and a method for manufacturing the semiconductor integrated circuit and a method for manufacturing the semiconductor device, and more particularly to an isolation used for the semiconductor integrated circuit or the semiconductor device, a sidewall spacer of a MOS transistor, wirings for connecting elements of the semiconductor integrated circuit, and layer insulation of the wirings.
2. Description of the Background Art
FIGS. 36 and 37
are typical views showing an example of a semiconductor integrated circuit having an isolation region according to the prior art.
FIG. 36
shows a planar layout of the semiconductor integrated circuit.
FIG. 37
shows a sectional structure taken along the line A—A in FIG.
36
.
A MOS transistor shown in
FIGS. 36 and 37
is a component of a semiconductor memory cell, for example.
In
FIGS. 36 and 37
, the reference numeral
1
denotes a semiconductor substrate, the reference numeral
2
denotes a shallow trench isolation (hereinafter referred to as an STI) which is provided by forming a trench having a depth of about 0.2 to 0.3 &mgr;m on the semiconductor substrate
1
and burying an insulator in the trench, the reference numerals
3
a
to
3
d
denote source/drain regions formed on a principal plane of the semiconductor substrate
1
, the reference numeral
4
denotes a gate oxide film stacked on the semiconductor substrate
1
or the STI
2
, the reference numeral
5
denotes a polysilicon gate electrode stacked on the gate oxide film
4
, the reference numeral
6
denotes a silicide film stacked on the polysilicon gate electrode
5
, the reference numeral
7
denotes an oxide film stacked on the silicide film
6
, the reference numeral
8
denotes a sidewall spacer formed on sidewalls of the gate oxide film
4
, the polysilicon gate electrode
5
, the silicide film
6
and the oxide film
7
, the reference numeral
11
denotes an interlayer film formed by covering the principal plane of the semiconductor substrate
1
, and the reference numeral
12
denotes a metal wiring formed on the interlayer film
11
. In this specification, the STI represents a method for isolating a set of elements which are adjacent to each other. In addition, the STI also represents a structure used for the isolating method. The STI
2
is formed in a peripheral portion of an active semiconductor region including the source/drain regions
3
a
to
3
d.
A MOS transistor formed by the source/drain regions
3
a
to
3
d,
the semiconductor substrate
1
, the gate oxide film
4
and the gate electrode
5
is used for a memory cell, for example.
The gate oxide film
4
, the polysilicon gate electrode
5
, the silicide film
6
, the oxide film
7
and the sidewall spacer
8
form signal lines
9
a
to
9
c.
Examples of a material of the silicide film
6
include tungsten silicide (WSi) and titanium silicide (TiSi). In general, the oxide film
7
is made of a silicon oxide film (SiO). The silicon oxide film has a resistivity of about 2×10
16
&OHgr;·cm.
A field transistor
10
shown in
FIG. 37
comprises the STI
2
, the wire
9
b
provided on the STI
2
, and the source/drain regions
3
b
and
3
c
provided on both sides of the STI
2
. The field transistor
10
is a parasitic transistor using a gate oxide film as the STI
2
.
Operation of a semiconductor memory cell is affected by the following properties:
1. Isolation characteristics;
2. Wiring capacitance;
3. Gate-to-source capacity and gate-to-drain capacitance; and
4. Stress applied to a gate electrode by formation of silicide.
The operation of the semiconductor memory cell is greatly affected by a quantity of a leak current and a magnitude of an allowable voltage between elements isolated in the isolation region which are included in the isolation characteristics listed in the item 1. It is desirable that the allowable voltage between the elements isolated in the isolation region should be greater and a smaller quantity of the leak current should flow between the elements through the isolation region.
As a method for obtaining such desirable isolation characteristics, it is proposed that a threshold voltage of the field transistor
10
parasitic in the isolation region should be increased. A threshold voltage V
th
of a MOS transistor formed by using a silicon substrate is calculated by Equation 1, wherein the threshold voltage is represented by V
th
, a Fermi level is represented by &phgr;
f
, a flat band voltage is represented by V
FB
, a gate capacitance is represented by C
0
, a dielectric constant of silicon is represented by K
S1
, a permittivity of a vacuum is represented by &egr;
0
, a unit charge is represented by q, an acceptor concentration is represented by N
A
, and a source-to-substrate voltage is represented by V
BS
. The dielectric constant K
Si
of the silicon is about 11.7.
V
th
=
2
φ
f
+
V
FB
+
1
C
0
2
K
Si
·
ϵ
0
·
q
·
N
A
·
2
φ
f
+
V
BS
(
1
)
The gate capacitance C
0
per unit area of the MOS transistor is calculated by Equation 2, wherein a dielectric constant of a silicon oxide film is represented by K
SiO2
and a thickness of a gate oxide film is represented by t
0x
. The dielectric constant K
SiO2
of the silicon oxide film is about 3.9.
C
0
=
K
SiO
2
·
ϵ
0
1
t
0
X
(
2
)
The gate oxide film of the field transistor
10
acts as the STI
2
. Therefore, as the dielectric constant of the STI
2
is reduced, the threshold voltage of the field transistor
10
is increased. After all, a dielectric constant of an insulator forming the STI
2
should be reduced in order to increase a voltage which can be isolated by the STI
2
and to decrease the quantity of the leak current.
In general, it is required that a size of a DRAM should be reduced according to a change of generation of the DRAM. In order to reduce an opening width of the STI
2
by a scaling law, a permittivity of the STI
2
should be decreased. The reason is as follows. It is required that an opening width of a trench should be reduced and a depth of the trench should be decreased if a shape of the STI
2
is to be changed by the scaling law. However, this requirement causes the isolation characteristics to be deteriorated. If the opening width of the trench is reduced and the depth of the trench is increased, it becomes hard to fill the trench with an insulator.
For example, Japanese Patent Application Laid-Open Gazette No. 8-46028 has disclosed that a trench is filled with a material whose dielectric constant is less than 3.3, that is, a polyimide or polymeric spin-on glass (SOG) in place of silicon dioxide (SiO
2
). However, it is difficult to fill the trench having a small opening width with an organic substance including a dielectric material such as the SOG. Furthermore, the disclosed element structure has no height difference between a semiconductor surface and a surface of the trench. Therefore, it is hard to perform mask alignment with high precision. For example, Japanese Patent Application Laid-Open Gazette No. 4-151850 has described an example in which a vacancy exists in a PSG (silicate glass) in an isolation trench. However, the vacancy described in the publication is generated by chance on only a part of the PSG in the isolation trench and is not intended to reduce a permittivity of the isolation trench. In particular, the invention described in the publication relates to a manufacturing method for preventing the vacancy formed on a bottom of the isolation trench from rising to a surface by reflow of the PSG, wherein the isolation trench is enlarged corresponding to the vacancy. A sectional area of the PSG through which an electric field is mainly transmitted is not reduced as compared with the prior art. Thus, the publication has not disclosed a method for manufacturing a semiconductor integrated circuit which can reduce the permittivity
Duy Mai Anh
Fahmy Wael
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
Method of forming an integrated circuit using an isolation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming an integrated circuit using an isolation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming an integrated circuit using an isolation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3020918