Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-12-06
2004-12-07
Nguyen, Van Thu (Department: 2824)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S239000
Reexamination Certificate
active
06828161
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit processing, and more particularly relates to an FeRAM structure and a method of manufacture thereof having a bottom electrode diffusion barrier that avoids a substantial undercut thereof during formation of the FeRAM capacitor.
BACKGROUND OF THE INVENTION
Several trends exist, today, in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and smaller and requiring less and less power. A reason for this is that more personal devices are being fabricated which are very small and portable, thereby relying on a small battery as its supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device that has a fair amount of memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device that retains its contents while a signal is not continuously applied to it is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (“EEPPROM”) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory that utilizes a ferroelectric material, such as SBT or PZT, as the capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for a FeRAM. The memory size and memory architecture affect the read and write access times of a FeRAM. Table 1 illustrates the differences between different memory types.
TABLE 1
FeRAM
Property
SRAM
Flash
DRAM
(Demo)
Voltage
>0.5
V
Read
>1
V
3.3
V
>0.5
V
Write
(12
V)
(±6
V)
Special
NO
YES
YES
NO
Transistors
(High Voltage)
(Low Leakage)
Write Time
<10
ns
100
ms
<30
ns
60
ns
Write
>10
15
<10
5
>10
15
>10
13
Endurance
Read Time
<10
ns
<30
ns
<30
ns/
60
ns
(single/
<2
ns
multi bit)
Read
>10
15
>10
15
>10
15
>10
13
Endurance
Added Mask
0
~6-8
~6-8
~3
for embedded
Cell Size
~80
F
2
~8
F
2
~8
F
2
~18
F
2
(F~metal
pitch/2)
Architecture
NDRO
NDRO
DRO
DRO
Non volatile
NO
YES
NO
YES
Storage
I
Q
Q
P
The non-volatility of an FeRAM is due to the bi-stable characteristic of the ferroelectric memory cell. Two types of memory cells typically are employed, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than a 1C memory cell.
As illustrated in prior art
FIG. 1
, a 1T/1C FeRAM cell
10
includes one transistor
12
and one ferroelectric storage capacitor
14
. A bottom electrode of the storage capacitor
14
is connected to a drain terminal
15
of the transistor
12
. The 1T/1C cell
10
is read from by applying a signal to the gate
16
of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor
14
to the source of the transistor (the bit line BL)
18
. A pulse signal is then applied to the top electrode contact (the plate line or drive line DL)
20
. The potential on the bit line
18
of the transistor
12
is, therefore, the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric material, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line
18
and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of the shown ferroelectric memory cell is that a read operation is destructive. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. The one difference from a DRAM is that a ferroelectric memory cell will retain its state until it is interrogated, thereby eliminating the need of refresh.
As illustrated, for example, in prior art
FIG. 2
, a 2T/2C memory cell
30
in a memory array couples to a bit line
32
and an inverse of the bit line (“bit line-bar”)
34
that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors
36
and
38
and two ferroelectric capacitors
40
and
42
, respectively. The first transistor
36
couples between the bit line
32
and a first capacitor
40
, and the second transistor
38
couples between the bit line-bar
34
and the second capacitor
42
. The first and second capacitors
40
and
42
have a common terminal or plate (the drive line DL)
44
to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors
36
and
38
of the dual capacitor ferroelectric memory cell
30
are enabled (e.g., via their respective word line
46
) to couple the capacitors
40
and
42
to the complementary logic levels on the bit line
32
and the bar-bar line
34
corresponding to a logic state to be stored in memory. The common terminal
44
of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell
30
to one of the two logic states.
In a read operation, the first and second transistors
36
and
38
of the dual capacitor memory cell
30
are enabled via the word line
46
to couple the information stored on the first and second capacitors
40
and
42
to the bar
32
and the bit line-bar line
34
, respectively. A differential signal (not shown) is thus generated across the bit line
32
and the bit line-bar line
34
by the dual capacitor memory cell
30
. The differential signal is sensed by a sense amplifier (not shown) that provides a signal corresponding to the logic level stored in memory.
A ferroelectric memory cell is limited to a finite number of read and write operations before the memory cell becomes unreliable. The number of operations that can be performed on a FeRAM memory is known as the endurance of a memory. The endurance is an important factor in many applications that require a nonvolatile memory. Other factors such as memory size, memory speed, and power dissipation also play a role in determining if a ferroelectric memory is viable in the memory market.
SUMMARY OF THE INVENTION
In essence, the instant invention relates to the fabrication of an FeRAM device which is either a stand-alone device or one which is integrated onto a semiconductor chip which includes many other device types. Several requirements either presently exist or may become requirements for the integration of FeRAM with other device types. One such requirement involves utilizing, as much as possible, the conventional front end and back end processing techniques used for fabricating the various logic and analog de
Aggarwal Sanjeev
Colombo Luigi
Martin J. Scott
Moise, IV Theodore S.
Summerfelt Scott R.
Brady III W. James
Garner Jacqueline J.
Luhrs Michael K.
Nguyen Van Thu
Telecky , Jr. Frederick J.
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