Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2009-05-15
2011-12-13
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
C438S655000
Reexamination Certificate
active
08076215
ABSTRACT:
A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.
REFERENCES:
patent: 5494835 (1996-02-01), Bruel
patent: 5527766 (1996-06-01), Eddy
patent: 5854123 (1998-12-01), Sato et al.
patent: 6174425 (2001-01-01), Simpson et al.
patent: 6316333 (2001-11-01), Bruel et al.
patent: 6727549 (2004-04-01), Doyle
patent: 6794276 (2004-09-01), Letertre et al.
patent: 6809009 (2004-10-01), Aspar et al.
patent: 6881644 (2005-04-01), Malik et al.
patent: 7180093 (2007-02-01), Takayama et al.
patent: 7183179 (2007-02-01), Droes et al.
patent: 7273788 (2007-09-01), Forbes
patent: 7348076 (2008-03-01), Locher et al.
patent: 7749884 (2010-07-01), Mathew et al.
patent: 2002/0055225 (2002-05-01), Gonzalez et al.
patent: 2004/0235268 (2004-11-01), Letertre et al.
patent: 2005/0061230 (2005-03-01), Kokta et al.
patent: 2005/0269617 (2005-12-01), Hofmann et al.
patent: 2006/0068565 (2006-03-01), Droes et al.
patent: 2006/0076559 (2006-04-01), Faure et al.
patent: 2006/0240275 (2006-10-01), Gadkaree
patent: 2007/0071900 (2007-03-01), Soussan et al.
patent: 2007/0249140 (2007-10-01), Dross et al.
patent: 2007/0269960 (2007-11-01), Letertre et al.
patent: 2008/0063840 (2008-03-01), Morita et al.
patent: 2009/0096003 (2009-04-01), Zhu
patent: 2010/0227475 (2010-09-01), Mathew et al.
patent: 2006-332681 (2006-12-01), None
patent: 2005/117123 (2005-12-01), None
International Search Report and Written Opinion dated Dec. 18, 2009 for PCT/US2009/043019.
International Search Report and Written Opinion dated Dec. 30, 2009 for PCT/US2009/044203.
Tong, Q.Y. et al. “A ‘smarter-cut’ approach to low temperature silicon layer transfer”; Appl. Phys. Lett. 72 (1), Jan. 5, 1998, American Institute of Physics, 1998, pp. 49-51.
Wolf, Stanley “2.10 Silicon-on-Insulator (SOI) Isolation Technologies”, Silicon Processing for the VLSI Era, vol. 2; Process Integration, Lattice Press, California, 1990, 66-78 pages.
Llona, L.D. Vargas et al. “Seedless Electroplating on Patterned Silicon”, J. Micromech, Microeng. 16, Journal of Micromechanics and Microengineering, IOP Publishing Ltd., May 8, 2006, pp. S1-S6.
U.S. Appl. No. 12/435,942, filed May 5, 2009.
U.S. Appl. No. 12/435,947, filed May 5, 2009.
Non-Final Office Action dated Oct. 5, 2009 from U.S. Appl. No. 12/435,942, filed May 5, 2009.
Notice of Allowance dated Mar. 25, 2010 from U.S. Appl. No. 12/435,942, filed May 5, 2009.
Non-Final Office Action dated Apr. 4, 2011 from U.S. Appl. No. 12/784,984, filed May 21, 2010.
Jawarani Dharmesh
Mathew Leo
AstroWatt, Inc.
Carpenter Robert
Richards N Drew
LandOfFree
Method of forming an electronic device using a separation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming an electronic device using a separation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming an electronic device using a separation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4261788