Etching a substrate: processes – Forming or treating electrical conductor article
Reexamination Certificate
1999-12-17
2002-06-04
Mills, Gregory (Department: 1763)
Etching a substrate: processes
Forming or treating electrical conductor article
C216S100000, C216S103000, C216S108000, C156S345110
Reexamination Certificate
active
06398974
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 1998-55646, filed on Dec. 17, 1998, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming an electrode for a thin film transistor, and more particularly to forming an electrode having a double-layered structure, consisting of first and second metal layers, by etching the metal layers in two steps varying the diluted density of an etching solution.
2. Discussion of the Related Art
In a liquid crystal display (hereinafter abbreviated LCD), thin film transistors (hereinafter abbreviated TFT) used as switching devices of driving devices and pixel electrodes transmitting or reflecting light are arranged in a matrix structure. Each of the TFTs and pixel electrodes constitutes a basic unit.
As the size of an LCD becomes larger, image distortion is caused by the delay of gate and data signals. In order to prevent the delays of the gate and data signals, the gate, source, and drain electrodes should be made of a metal having a low resistance, such as Al and the like.
Yet, hillock and junction spiking are generated if the gate, source, and drain electrodes are formed with Al. Therefore, the electrodes are constructed with two layers such that a refractory metal lies on an Al layer, specifically the refractory metal Mo or an alloy of Mo, such as MoW, MoTa, MoNb, and the like.
FIGS. 1A
to
1
C show a method of forming an electrode of a TFT according to a related art.
Referring to
FIG. 1A
, first and second metal layers
13
and
15
respectively are formed on a substrate
11
. The first metal layer
13
is made of a metal having a low resistance, such as Al and the like, and the second layer
15
is made of Mo or an alloy of and Mo, such as MoW, MoTa, MoNb, and the like. The metal layers
13
and
15
are deposited successively by chemical vapor deposition (hereinafter abbreviated CVD) or by sputtering.
In this case, the substrate
11
is an insulated substrate made of an insulated material such as glass, quartz, transparent plastic, or the like. Also, the substrate
11
may include an insulating layer of silicon oxide, silicon nitride, or the like formed on the insulated substrate.
A photoresist pattern
17
is formed by coating the second metal layer
15
with photoresist, then by patterning the photoresist to remain on only a predetermined portion of the second metal layer
15
by exposure and development.
Referring to
FIG. 1B
, an electrode
19
is formed by etching the second and first metal layers
15
and
13
using the photoresist pattern
17
as an etch mask to expose the substrate
11
. In this case, the electrode
19
is formed by etching the second and first metal layers
15
and
13
with an etching solution mixed with (H
3
PO
4
0
+HNO
3
+CH
3
COOH +H
2
O), or another solution of (H
3
PO
4
O+HNO
3
+CH
3
COOH+H
2
O) mixed with deionized water, which is diluted by a mixing ratio equal to or less than 1:2.
Referring to
FIG. 1C
, the photoresist pattern
17
on the electrode
19
is removed by ashing. Thus, the electrode
19
remaining on the substrate
11
becomes a gate, source, or drain electrode.
In accordance with the related art, the electrode is formed by etching the second and first metal layers with an etchant of an etching solution mixed with (H
3
PO
4
O+HNO
3
+CH
3
COOH+H
2
O) only, or another solution of (H
3
PO
4
O+HNO
3
+CH
3
COOH+H
2
O) mixed with deionized water, which are diluted by a mixing ratio equal to or less than 1:2.
Unfortunately, the method of forming an electrode of the related art may cause hillock and junction spiking as the exposed surface of the second metal layer is broadened by using the etching solution mixed with (H
3
PO
4
O+HNO
3
+CH
3
COOH+H
2
O) only, or another solution of (H
3
PO
4
O÷HNO
3
+CH
3
COOH+H
2
O) mixed with deionized water, which is diluted by a mixing ratio less than 1:2. This is because the etch rate of the second metal layer is 4 to 5 times faster than that of the first metal layer.
Moreover, when the quantity of the mixed solution of (H
3
PO
4
O+HNO
3
+CH
3
COOH+H
2
O) exceeds that of deionized water, undercutting is generated since the etch rate of the first metal layer is faster than that of the second metal layer.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for forming an electrode for a thin film transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of fabricating en electrode which prevents hillock and junction spiking and also controls undercutting.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims, as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method according to the present invention includes: forming first and second metal layers successively on a substrate; forming a photoresist pattern on a predetermined portion of the second metal layer; etching the second metal layer to expose the first metal layer with a dense mixed solution of (H
3
PO
4
O+HNO
3
+CH
3
COOH+H
2
O), using the photoresist pattern as an etch mask; etching the exposed first metal layer with a diluted mixed solution of (H
3
PO
4
O+HNO
3
+CH
3
COOH+H
2
O), using the photoresist pattern as an etch mask; and removing the photoresist pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 3833434 (1974-09-01), Kikushi et al.
patent: 4283248 (1981-08-01), Kakuhashi et al.
patent: 5059278 (1991-10-01), Cohen et al.
patent: 5464500 (1995-11-01), Tsujimura et al.
patent: 5639344 (1997-06-01), Konuma et al.
Hassanzadeh P.
LG. Philipslcd Co., Ltd.
Long Aldridge & Norman LLP
Mills Gregory
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