Method of forming an electrical connection

Details Method of forming an electrical connection Method of forming an electrical connection

1994-04-28

1995-07-18

Hearn, Brian

Fishing, trapping, and vermin destroying

437186, 437193, 437233, H01L 21441

Patent

active

054341035

ABSTRACT:
An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

REFERENCES:
patent: 4966864 (1990-10-01), Pfiester
patent: 4994400 (1991-02-01), Yamaguchi et al.
patent: 5015599 (1991-05-01), Verhaar
patent: 5026663 (1991-06-01), Zdebel et al.
Colinge, J. P. et al.; "Silicon-On-Insulator `Gate-All-Around Device", IEEE, IEDM 90-595-599 (1990).
Tanaka, T. et al.; "Analysis of P.sup.+ PolySi Double-Gate Thin-Film SOI MOSFETS", IEEE, IEDM 91-683-686, (1981).

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