Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-09-14
2002-07-16
Ho, Hoai V. (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S106000, C257S738000
Reexamination Certificate
active
06420208
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to integrated circuits and more particularly to a substrate to die interface used in assembled integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are formed on semiconductor substrates (wafers) using a number of different processing operations that create the circuit elements. The circuit elements consist of transistors, resistors, capacitors, interconnects, and other functional structures. In practice, multiple die, circuit arrays for a specific function, are formed on a semiconductor substrate and are cut (scribed or sawn) from the substrate to form single die ready for attachment to a package or other interface. Access to the die circuitry is made from the package or interface contacts to bond pads formed on the final metal layer of the die. Bond pads provide the means for transfer of electrical signals and power from and to the die via bonding wires, conductive bumps, etc., connected to the package or interface substrate. The package or wiring board substrate (direct chip- attach to board, or multi-die package substrate) is the connection between the die and other circuits. In the case of flip chip packaging the die has metal balls formed on the bond pads and is flipped onto complementing bond pads of the package substrate. Thermal processing of the die/package sandwich completes the contact. The electrically conductive balls and an under-fill adhesive applied between the die and package substrate provide adherence of the die to the package. In addition, an adhesive fillet is applied to the sides of the die to add to the robustness of the die to package substrate attach.
A problem with cost and complexity arises when a backside ground contact is needed for a flip chip packaged die. The backside electrical ground connects the backside of the wafer to a common electrical potential, the ground potential, which is generally considered to be the null reference potential. In the case of silicon on insulator (SOI) semiconductor substrates, the silicon where the transistors are made is separated from the backside of the substrate by a layer of buried oxide. Conventionally, to form a ground contact to the backside, interconnects are added to connect to via openings through the silicon and buried oxide to the backside in each die. The formation of this contact requires additional processing of at least one mask-layer and an etch step. In-package solutions include attachment of a grounded heat sink or deposition of a metal film on the backside that is wire bonded to a ground contact, each of which require additional processing and hardware costs.
In order to realize minimum complexity the present disclosure provides an alternative ground contact for packaged die. Conventionally, the die is formed when the wafer is sawn into pieces along the scribe street. The edge of the kerf from this cut forms the die edge which is normally covered by non-conductive fillet material after the die is mounted in the package. The present invention uses a conductive fillet that contacts the side of the sawn die, the ground pad on the package substrate, and/or the metal from the edge seal exposed at the sawn edge of the die. The edge seal is an existing interconnect feature that parallels the perimeter of the die at all levels such that it forms a barrier on the edge of the die. As disclosed herein, in order to provide an electrical ground for the back contact, the edge seal has metal fingers or interconnected tiles extending from every metal layer into the saw street such that the saw process exposes this metal. In addition, a row of metal pads or a line(s) that lies, at or just outside the perimeter of the attached die maybe added to the package substrate to provide an electrical ground for the backside fillet contact. Connection to the backside silicon, the exposed edge seal fingers, and/or the package perimeter contact is made by an electrically conductive fillet material, such as metal filled epoxy, for example. The conductive fillet material replaces the standard nonconductive fillet material typically used in die packaging.
The advantages of this alternative method of forming a ground contact is that no special wafer processing is necessary, no additional interconnects are needed, and process induced gate damage by differential charging of the backside of the wafer is eliminated. Fillet contact to the edge of the bulk silicon is sufficient to allow electric charge to bleed off without additional processing. All steps are standard except for the substitution of fillet material and a minor mask change at the metal levels. The grounded fillet around the perimeter of the die also forms a partial radiofrequency (RF) shield that can be made complete by attachment of a heat sink and the addition of ground planes to the package substrate.
An additional benefit of the structure described herein is the removal of heat from the die laterally using the edge seal and the fillet contact. Metal interconnects and ground lines or planes connected to the edge seal would conduct heat to a thermally as well as electrically conductive fillet. The fillet heat sink also provides an additional conduction path from the fillet to an external heat sink thus increasing the ability to remove heat.
REFERENCES:
patent: 5977633 (1999-11-01), Suzuki et al.
Downey Harold A.
Kobayashi Thomas S.
Pozder Scott K.
Clingan, Jr. James L.
Ho Hoai V.
Le Dung Anh
Motorola Inc.
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