Etching a substrate: processes – Forming or treating electrical conductor article
Reexamination Certificate
2000-10-18
2004-03-02
Alanko, Anita (Department: 1765)
Etching a substrate: processes
Forming or treating electrical conductor article
C216S017000, C216S051000, C216S052000, C216S100000, C216S105000, C029S847000, C219S121690, C219S121710
Reexamination Certificate
active
06699395
ABSTRACT:
TECHNICAL FIELD
The invention relates to an improved method for forming alignment features on conductive devices.
BACKGROUND ART
An important and continuing goal in the computer and electronics industries is that of increasing conductive or signal trace density and bandwidth of conductive devices, such as printed circuit boards (PCB's). A limiting factor for increasing the trace density is the ability to properly align the traces of one PCB with the traces of another PCB when the PCB's are electrically joined together. In order to align the traces of the PCB's, alignment features are typically formed on each PCB.
A prior method of forming a PCB with such alignment features includes forming a plurality of traces on a substrate. The PCB is then inserted into a drilling device, and a drill bit of the drilling device is optically aligned with contact portions of the traces. Next, the drill bit is used to form a plurality of mechanical alignment features such as holes in the board. The holes may then be used to pin the PCB to another PCB having similar holes so as to align the contact portions of the PCB's.
Because the mechanical alignment features are formed separately from the traces, it is difficult to obtain precise registration of the mechanical alignment features with the contact portions of the traces.
DISCLOSURE OF INVENTION
The invention addresses the shortcomings of the prior art by providing an improved method of forming a conductive device having one or more mechanical alignment features that are aligned with conductive traces of the device.
Under the invention, a method of forming a conductive device includes forming a conductive layer on a substrate; etching the conductive layer to form a plurality of conductive traces; etching the conductive layer to form at least one mask feature; and removing substrate material that is not covered by the at least one mask feature so as to form at least one mechanical alignment feature.
Preferably, the forming steps are performed simultaneously by a photo-etching process. As a result, precise registration between the at least one mask feature and the contact portions can be achieved.
Advantageously, the method of the invention may be used to form various configurations of the at least one alignment feature. For example, the at least one alignment feature may be formed as a hole, a side edge, a tab and/or a slot.
More specifically, a method under the invention of forming a printed circuit board includes forming a conductive layer on a substrate; etching the conductive layer to form multiple conductive traces, each trace having a contact portion; etching the conductive layer to form multiple mask features that cooperate to define a template; and ablating with a laser substrate material that is not covered by the template so as to form a plurality of mechanical alignment features.
REFERENCES:
patent: 3401369 (1968-09-01), Palmateer et al.
patent: 3663920 (1972-05-01), Lapham et al.
patent: 3796986 (1974-03-01), Tamburro
patent: 4513064 (1985-04-01), Marcus
patent: 4631100 (1986-12-01), Pellegrino
patent: 4660920 (1987-04-01), Shibano
patent: 4816427 (1989-03-01), Dennis
patent: 4871315 (1989-10-01), Noschese
patent: 4940413 (1990-07-01), Childers et al.
patent: 4991290 (1991-02-01), MacKay
patent: 5046954 (1991-09-01), Schmedding
patent: 5163835 (1992-11-01), Morlion et al.
patent: 5175409 (1992-12-01), Kent
patent: 5176524 (1993-01-01), Mizuno et al.
patent: 5219292 (1993-06-01), Dickirson et al.
patent: 5252784 (1993-10-01), Asai et al.
patent: 5261826 (1993-11-01), Leeb et al.
patent: 5284725 (1994-02-01), Takatsu
patent: 5336095 (1994-08-01), Walburn et al.
patent: 5343616 (1994-09-01), Roberts
patent: 5345364 (1994-09-01), Biernath
patent: 5373109 (1994-12-01), Argyrakis et al.
patent: 5383788 (1995-01-01), Spencer
patent: 5418691 (1995-05-01), Tokura
patent: 5442170 (1995-08-01), Kreft et al.
patent: 5451261 (1995-09-01), Fujii et al.
patent: 5521992 (1996-05-01), Chun et al.
patent: 5582745 (1996-12-01), Hans et al.
patent: 5643835 (1997-07-01), Chia et al.
patent: 5731047 (1998-03-01), Noddin
patent: 5741148 (1998-04-01), Biernath
patent: 5764497 (1998-06-01), Mizumo
patent: 5808529 (1998-09-01), Hamre
patent: 5827084 (1998-10-01), Biernath
patent: 5917149 (1999-06-01), Barcley et al.
patent: 5971806 (1999-10-01), Evans et al.
patent: 6012221 (2000-01-01), Campbell
patent: 6139360 (2000-10-01), Hayashi et al.
patent: 6431876 (2002-08-01), Svenkeson et al.
patent: 6438281 (2002-08-01), Tsukamoto et al.
patent: 6508674 (2003-01-01), Svenkeson et al.
patent: 3932277 (1990-04-01), None
patent: 01209794 (1989-08-01), None
patent: 04186731 (1992-07-01), None
patent: WO 99/30542 (1999-06-01), None
IBM Technical Disclosure Bulletin, NN81034466, “Embedded Reference or Voltage Plane for Metallized Ceramic Substrate” 23 (10), pp 4466-4467, Mar. 1981.*
U.S. patent application Ser. No. 09/690,791, Svenkeson et al., filed Oct. 2000.
U.S. patent application Ser. No. 09/690,561, Svenkeson et al., filed Oct. 2000.
U.S. patent application Ser. No. 09/690,348, Svenkeson et al., filed Oct. 2000.
Hamre John D.
Svenkeson John W.
Alanko Anita
Brooks & Kushman P.C.
Storage Technology Corporation
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