Method of forming a zero layer mark for alignment in integrated

Details Method of forming a zero layer mark for alignment in integrated Method of forming a zero layer mark for alignment in integrated

1997-01-28

1999-04-13

Fourson, George

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

438427, 438734, 438975, H01L 2176

Patent

active

058937447

ABSTRACT:
A method of forming an alignment mark in a wafer during the manufacture of shallow isolation trenches for semiconductor devices provides a nitride layer on a substrate prior to the formation of the alignment mark. Once the nitride layer has been formed, etching is performed to create the alignment mark in the substrate. Further processing steps of the shallow trench isolation technique do not require the depositing of nitride into the alignment mark. Since the alignment mark is etched only after the nitride layer has been deposited, no further nitride enters into the alignment mark and a nitride-free alignment mark is provided.

REFERENCES:
patent: 4737468 (1988-04-01), Martia
patent: 5157003 (1992-10-01), Tsuji et al.
patent: 5179038 (1993-01-01), Kinney et al.
patent: 5578519 (1996-11-01), Cho
patent: 5646063 (1997-07-01), Mehta et al.
patent: 5733801 (1998-03-01), Gojohbori
patent: 5817568 (1998-10-01), Chao

Affiliated with

Also associated with

Rating

Method of forming a zero layer mark for alignment in integrated does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a zero layer mark for alignment in integrated , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a zero layer mark for alignment in integrated will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-222204