Method of forming a via plug in a semiconductor device

Details Method of forming a via plug in a semiconductor device Method of forming a via plug in a semiconductor device

1994-09-15

1995-04-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437192, 437203, 148DIG138, H01L 2144

Patent

active

054098610

ABSTRACT:
A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.

REFERENCES:
patent: 5198389 (1992-02-01), DeBakker et al.
patent: 5232872 (1993-08-01), Ohba
patent: 5270256 (1993-12-01), Bost et al.
patent: 5320979 (1994-06-01), Hashimoto et al.

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