Registers – Records
Reexamination Certificate
2000-10-20
2002-09-10
Frech, Karl D. (Department: 2876)
Registers
Records
C438S258000, C257S767000, C257S382000, C257S774000, C257S296000
Reexamination Certificate
active
06446873
ABSTRACT:
BACKGROUND
1. Field
The present invention is related to semiconductor or silicon fabrication technology, and, more particularly, to forming a via overlap.
2. Background Information
As is well-known, in the process of forming an integrated circuit chip, typically, layers are formed on top of a semiconductor substrate. Of course, although silicon is typically employed, other semiconductors, such as germanium or gallium arsenide; may, of course, be used. The layers typically include an insulating material, such as oxide, with metal routing or metallization being employed to interconnect different transistors or other components embedded in the silicon. Additional background information about semiconductor fabrication technology is provided, for example, in “CMOS Processing Technology,” Chapter 3 of
Principles of CMOS VLSI Design
, by Neil Weste and Kamran Eshraghian, available from Addison-Wesley Publishing Company, Second Edition, 1993.
In order to form the metal interconnect, holes are formed through the oxide in order to contact portions of the components or transistors, such a polysilicon gate or landing site, for example. These holes are referred to as vias. In designing or laying out such chips, the density of the chip is affected, at least in part, by how well the metal lines and vias are distributed to interconnect the components or the transistors. It is desirable to have the interconnect portion of the chip be as dense with metal routing as is feasilbe. The higher the density of the metal routing, the less power employed to drive the circuitry, due to shorter metal lines, that reduce the resistance and capacitance associated with the metal. Likewise, a more dense metal interconnect may reduce the size of the die, which reduces cost and silicon. Therefore, it is desirable to continue to come up with techniques to fabricate integrated circuit chips that result in higher density interconnects.
SUMMARY
Briefly, in accordance with one embodiment of the invention, a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides.
Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides.
Briefly, in accordance with still another embodiment of the invention, an integrated cicuit includes: a semiconductor substrate, the semiconductor substrate having formed thereon an interconnect. The interconnect including at least two vias, the at least two vias being located diagonally with respect to one another and each having a metal overlap with a polygon shape of more than four sides.
REFERENCES:
patent: 4196443 (1980-04-01), Dingwall
patent: 4951101 (1990-08-01), Alter et al.
patent: 5432381 (1995-07-01), Melzner
patent: 5508564 (1996-04-01), Lee et al.
patent: 6166441 (2000-12-01), Geryk
patent: 6297557 (2001-10-01), Bothra
patent: 6300197 (2001-10-01), Inaba
patent: 189739 (1998-07-01), None
Frech Karl D.
Intel Corporation
Sanders Allyson N
Skaist Howard A.
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