Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-11-20
2001-07-31
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
69
Reexamination Certificate
active
06268263
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a method of manufacturing a semiconductor device, and the device. More specifically, the present invention relates to a technique for planarizing a film on a semiconductor substrate having a trench type element isolation structure.
2. Background of the Invention
A semiconductor integrated circuit needs to avoid electrical interference between elements to control them independently in operation. For this reason, the semiconductor integrated circuit has adopted the element isolation structure having an element isolation region. One of well-known methods for forming such a structure is a trench isolation method, to which various improvements have been proposed.
The trench isolation method is a method for providing electrical isolation between elements by forming a trench in a substrate from the surface and filling the trench with a dielectric. This method causes little bird's beak that is found in a structure formed by a LOCOS method, thereby reducing the area of the element isolation structure on the substrate surface as compared with the LOCOS method. Thus, the trench isolation method is suitable for promoting downsizing of a semiconductor integrated circuit. That is, it can be said that the method is an indispensable element isolation method for a semiconductor device which will be more downsized.
In a manufacturing process of a downsized, multi-layer integrated circuit, with a reduction in focus margin in the photolithography process or a reduction in overetching in the etching process, it becomes important to ensure flatness of each layer formed on the substrate. For this reason, a CMP method has been widely performed to planarize the top surface of the substrate after the trench type element isolation structure is formed.
Before planarization by the CMP method, for the purpose of reducing polishing time and avoiding over-polishing (dishing) in a large element isolation region, dry etching is often applied to a large protrusion on the surface previous to the polishing by the CMP method. Such preliminary planarization is hereinafter referred to as “first planarization”, while the planarization by the CMP method as “second planarization”. A planarization technique which combines the first and the second planarization, can be said a simple and effective technique for high-precision planarization.
To achieve element isolation by the trench isolation method, it is necessary to fill a narrow-opened trench with a dielectric without “key-hole” shaped cross-sectional void (seam). One of outstanding methods to meet this requirement is a film formation method, such as an HDP-CVD (High Density Plasma-Chemical Vapor Deposition), that performs etching and deposition at the same time. In the following description, we take the HDP-CVD method as an example.
A film formed by the HDP-CVD method has a characteristic section shape as described later. Thus, it is impossible to employ first planarization according to a conventional technique, as it is, that is given for planarizing a film formed by a film formation method such as a low-pressure CVD method (disclosed, for example, in Japanese Patent Laid-Open No. 9-102539). To resolve this problem, various propositions have been made. We will now described such propositions, referring to the drawings.
FIGS. 21
to
28
are longitudinal cross-sectional views of a semiconductor device, showing successive stages of a method for manufacturing the device according to a first conventional technique.
As shown in
FIG. 21
, a silicon substrate
101
, on which (on a surface
101
S) a silicon oxide film (or underlying oxide film)
102
and a silicon nitride film
103
are sequentially formed, is etched to form trenches
121
A and
121
C (each referred to also as a trench
121
) that form element isolation regions
120
A and
120
C (each referred to also as an element isolation region
120
), respectively. More specifically, with a photolithography pattern used as a mask, the silicon nitride film
103
and the silicon oxide film
102
are anisotropically etched to form the trenches
121
in the silicon substrate
101
from the surface
101
S to a predetermined depth. In the drawing, regions except the element isolation regions
120
are active regions
130
B and
130
D (each referred to also as an active region
130
). The concept of the element isolation regions
120
and the active regions
130
includes not only a two-dimensional region on the surface
101
S of the silicon substrate
101
but also a three-dimensional region in a direction perpendicular to the surface
101
S of the silicon substrate
101
.
In the following drawings, when there is a necessity to distinguish between each of the element isolation regions
120
or between each of the active regions
130
, an additional English alphabet is attached to the reference numeral of each region, for example, the element isolation regions
120
A,
120
C or the active regions
130
B,
130
D as shown in FIG.
21
. Similarly, the same component in each element isolation region
120
or in each active region
130
is distinguished by attaching the alphabet of each region to the reference numeral thereof.
Next, as shown in
FIG. 22
, silicon oxides
111
are formed on the overall surface by the HDP-CVD method, by which the trenches
121
A and
121
C are filled with silicon oxides
111
A and
111
C, respectively. Each of the silicon oxides
11
A and
111
C buried in the trenches
121
A and
121
C is referred to also as a “buried oxide
111
”, while each of silicon oxides
111
B and
111
D formed on the silicon nitride films
103
B and
103
D, respectively, is referred to also as a “silicon oxide film
111
”. The silicon oxide films
111
B and
111
D have characteristic shapes due to the properties of film formation by the HDP-CVD method. That is, the silicon oxide films
111
are formed to be protrusions having triangular or trapezoidal section shapes, depending on the width of the active regions
130
. The slope of such protrusions from the edges of the active regions
130
has a gradient of about 45° to the substrate surface
101
S. Thus, a trapezoidal silicon oxide film
111
D is formed on the silicon nitride film
103
D in the active region
130
D which has a width of twice the thickness of the silicon oxide film
111
D.
Next, a resist is formed on the overall surface of the silicon oxides
111
. The resist is then patterned by photolithography to form a resist
141
having a pattern shown in FIG.
23
. More specifically, as shown in
FIG. 23
, the resist
141
is formed to cover the silicon oxides (buried oxides)
111
in all the element isolation regions
120
, and the silicon oxide films
111
in the active regions
130
that range from each edge of the element isolation regions
120
to a distance equivalent to the maximum film thickness of the silicon oxide films
111
(or film thickness of the buried oxides
111
). Further, if the opening width of the resist
141
in the active region
130
is smaller than the minimum design size of the semiconductor device (e.g., the active region
130
B in FIG.
23
), the resist
141
is further formed on the silicon oxide film
111
in that active region.
Then, the silicon oxide film
111
that is not covered with the resist
141
is dry etched, with the silicon nitride film
103
used as a stopper film. That is, the silicon oxide film
111
D of the maximum film thickness h on the silicon nitride film
103
D is etched back. This completes the first planarization of the silicon oxide film
111
(see FIG.
24
).
After that, the resist
141
is removed to expose the silicon oxide films
111
covered with the resist (see FIG.
25
).
Next, the exposed silicon oxide films
111
(including the remainder of the silicon oxide film
111
D), shown in
FIG. 25
, are polished and removed by the CMP method (second planarization). In planarization by the CMP method, a stopper film is generally provided at the end of polishing. When a silicon oxide film is a film to be polished, a sil
Horita Katsuyuki
Kuroi Takashi
Sakai Maiko
Le Vu A.
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Pyonin Adam
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