Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1995-06-28
2001-10-23
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S430000, C438S437000, C438S387000
Reexamination Certificate
active
06306724
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to semiconductor fabrication processes and more particularly to a method of forming a trench isolation structure in a stack trench capacitor fabrication process.
BACKGROUND OF THE INVENTION
Trench isolation structures have received increasing use in integrated circuit device fabrication in order to improve operating characteristics of the integrated circuit device. However, as the need for smaller device size increases, isolation spaces must also be smaller in order to take advantage of the smaller device fabrication techniques. Conventional trench isolation structures are fabricated through LOCOS techniques. However, LOCOS isolation cannot be decreased to lithographic limits. Therefore, it is desirable to have a method of forming a trench isolation structure that can be scaled down to lithographic limits.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a trench isolation structure process with a decreased isolation space size. A need has also arisen for a trench isolation process that can be scaled down to lithographic limits.
In accordance with the present invention, a method of forming a trench isolation structure in a stack trench capacitor fabrication process is provided which substantially eliminates or reduces disadvantages and problems associated with conventional trench isolation structure processes.
According to an embodiment of the present invention, there is provided a method of forming a trench isolation structure in a stack trench capacitor fabrication process that includes forming an interface layer onto a semiconductor substrate and forming a buffer layer onto the interface layer. A trench region is formed through the buffer layer, the interface layer, and into the semiconductor substrate. A trench wall layer is formed on the interior walls of the trench region and is in contact with the remaining interface layer on the semiconductor substrate. A trench filler layer is formed within the trench region on the trench wall layer. A storage dielectric is formed on the trench filler layer and within the trench region followed by the forming of a field plate layer on the storage dielectric and within the trench region. A trench cap layer is formed on the field plate layer such that the trench filler layer, the storage dielectric, and the field plate layer are surrounded by the trench cap layer and the trench wall layer.
The method of the present invention provides various technical advantages over conventional trench isolation structure processes. For example, one technical advantage is in forming a trench isolation structure through the use of a stack trench capacitor fabrication process. Another technical advantage is in forming a trench isolation structure with a small isolation space as compared to conventional processes. Yet another technical advantage is in forming a trench isolation structure that is scaled down to lithographic limits. Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
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Brady III W. James
Dang Trung
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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