Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-03-26
2003-07-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S430000, C438S435000, C438S524000
Reexamination Certificate
active
06589853
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor device and method of manufacturing the same and more particularly to a semiconductor device that may have an insulating film embedded in a concave portion formed in a semiconductor substrate and a method of forming the same.
BACKGROUND OF THE INVENTION
It is a continuing goal to increase the integration level of semiconductor devices. In order to do so, it is desirable to make device structures and device isolation structures smaller. One method of providing smaller device isolation structures is to use a trench isolation structure in place of a conventional local oxidation of silicon (LOCOS) method.
A conventional trench isolation method will now be described with reference to
FIGS. 7 and 8
. The conventional trench isolation method includes forming a concave portion or trench inside a semiconductor substrate. The trench is etched in a silicon substrate to a depth required for isolation between adjacent devices, forming an insulating film to fill the trench, and then removing the insulating film located outside the trench with a flattening step.
FIGS. 7 and 8
are cross-sectional diagrams of a conventional trench isolation structure after various process steps.
Referring now to FIG.
7
(
a
), a silicon oxide film
102
and a silicon nitride film
103
are formed sequentially on a silicon substrate
101
. Next, a resist pattern (not shown) is formed and etched to expose silicon nitride film
103
located over a region (non-active region) where a trench is to be formed. Then, using the resist pattern as a mask, silicon nitride film
103
and silicon oxide film
102
are etched sequentially until the surface of silicon substrate
101
is exposed. The resist pattern is then removed, the exposed silicon substrate
101
is etched using silicon nitride film
103
as a mask to form a trench T.
Referring now to FIG.
7
(
b
), a thermal oxide film
104
is formed on the inner wall surface of trench T. Thermal oxide film
104
helps to compensate for damage to the surface of the substrate
101
caused the above-mentioned etching carried out to form trench T. Thermal oxide film
104
also helps to prevent dislocation from occurring inside the substrate
101
by rounding off the corners of trench T to relieve stress.
Referring now to FIG.
7
(
c
), a nitride film liner
105
is then formed over the surface and an embedding insulating film
106
is then formed on the surface to fill trench T. Nitride film liner
105
is formed to prevent oxygen from infiltrating inside the wall of trench T through embedding insulating film
106
in a subsequent oxidation step, or the like. In this way, the trench walls may be prevented from being further oxidized. If oxygen infiltrates the wall of trench T, silicon in that portion is oxidized and increases in volume to produce stress. This can cause defects such as dislocation, or the like, which can cause device characteristics to deteriorate.
Referring now to FIG.
8
(
a
), chemical mechanical polishing (CMP) is carried out until silicon nitride film
103
is exposed to flatten the surface of the substrate.
Referring now to FIG.
8
(
b
), silicon nitride film
103
formed over the region (active region) other than the non-active region of the substrate
101
is removed by wet etching. At this time, if the thickness of nitride film liner
105
is thick, nitride film liner
105
is etched deep inside the trench. As will be illustrated later, this causes a groove to be formed in this region in a subsequent step.
Referring now to FIG.
8
(
c
), silicon oxide film
102
over the active region and a protruding portion of embedding insulating film
106
in the non-active region are removed in a wet washing step (wet etching) to form a target trench isolation structure. At this time, a groove D is formed along the edge of the device isolation region (trench isolation region) formed with the insulating film embedded in the trench. Groove D is caused due to a part of nitride film liner
105
being etched inside the trench (illustrated in FIG.
8
(
b
)).
When groove D is deep and/or wide, an electrically conductive material tends to remain inside groove D in a later step of forming gate electrode. This can cause short circuit failure in these gate electrodes. Also, the electric field of the gate electrodes can be increased in the substrate corners defined by groove D. Such an increased electric field causes instability in device characteristics, such as threshold voltage, which causes undesirable effects such as an increase of leakage currents, or the like. In order to suppress the formation of groove D, it is desirable that nitride film liner
105
has a relatively thin film thickness.
Japanese Patent Application Laid-Open No. 2000-12677 (JPA 12677) describes a method of forming a conventional trench isolation structure such that groove D may be suppressed. A conventional trench isolation structure disclosed in JPA 12677 will be discussed with reference to
FIGS. 9 and 10
.
Referring now to FIG.
9
(
a
), silicon oxide film
102
and silicon nitride film
103
are formed on substrate
101
. Silicon nitride film
103
is then patterned and etched. Etching the exposed surface of substrate
101
to form trench T is done in the same manner as the conventional approach illustrated in FIG.
7
(
a
). Thermal oxide film
104
is then formed on an inner wall of trench T in the same manner as previously described and illustrated in FIG.
7
(
b
).
Referring now to FIG.
9
(
b
), silicon nitride film
103
is isotropically etched by a predetermined thickness. By isotropic etching, not only the upper surface of silicon nitride film
103
, but also lateral surface portions are etched. In this way, the diameter of the opening in silicon nitride film
103
is enlarged with respect to that of trench T. As a result, a brim-like portion where the surface of substrate
101
or oxide film
102
is exposed around the opening portion of trench T and a step-like shape is obtained.
Referring now to FIG.
9
(
c
), nitride film liner
105
is formed on the surface of substrate
101
in the same manner as previously described and illustrated in FIG.
7
(
c
). Then, embedding insulating film
106
is formed so as to fill the inside of trench T.
Referring now to FIG.
10
(
a
), CMP is carried to planarize the surface and expose the silicon nitride film
103
in the same manner as previously discussed and illustrated in FIG.
8
(
a
).
Referring now to FIG.
10
(
b
), silicon nitride film
103
is removed by isotropic etching (wet etching). During the isotropic etching, nitride film liner
105
is also gradually removed from the exposed edge. However, because the brim-like portion serves as a buffer, excessive etching which reaches the inside of the trench is prevented even though nitride film liner
105
on the brim-like portion is removed by etching. Thus, groove D is prevented from being formed in the wet washing step and trench isolation structure is formed as illustrated in FIG.
10
(
c
).
The above-mentioned JPA 12677 reference discloses an alternative way of forming a brim-like portion around the opening edges of trench T in another embodiment as will be discussed with reference to FIG.
11
.
Referring now to FIG.
11
(
a
), after silicon oxide film
102
and silicon nitride film
103
are sequentially etched to form an opening so as to expose a surface silicon substrate
101
in an inactive region, an oxide film is formed on the entire surface. The oxide film is then etched back by anisotropic etching to form spacers
107
on lateral walls of the opening.
Referring now to FIG.
11
(
b
), the exposed portion of substrate
101
is etched using spacers
107
and silicon nitride film
103
as masks to form trench T.
After removal of spacers
107
, a thermal oxide film is formed on the inner wall of trench T. In this way, a step-like shape similar to that illustrated in FIG.
9
(
b
) is obtained where a brim-like portion is formed around the opening portion of the trench T.
In order to ensure a sufficient width in th
Isaac Stanetta
NEC Electronics Corporation
Niebling John F.
Sako Bradley T.
Walker Darryl G.
LandOfFree
Method of forming a trench isolation structure having a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a trench isolation structure having a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a trench isolation structure having a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3080656