Method of forming a trench capacitor for a DRAM cell

Details Method of forming a trench capacitor for a DRAM cell Method of forming a trench capacitor for a DRAM cell

1998-01-26

2000-08-22

Fahmy, Wael

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

438390, 257301, H01L 2110

Patent

active

061071536

ABSTRACT:
A method for forming a trench capacitor of a dynamic random access memory cell is disclosed. The method includes patterning to etch a semiconductor substrate (10) of a first conductivity to form a trench (18) in the substrate. Ions of the first conductivity are tilt-implanted over the trench, so that sidewalls and a bottom surface of the substrate near the trench are doped with the ions of the first conductivity. Next, first ions of a second conductivity are tilt-implanted over the trench at a first angle, thereby forming a first implanted region (22), followed by tilt-implanting second ions of the second conductivity over the trench at a second angle, thereby forming a second implanted region (24). The first angle is larger than the second angle, and the first implanted region and the second implanted region together form a bottom cell plate of the trench capacitor. Finally, a dielectric layer (26) is formed on the bottom plate of the trench capacitor, and a conductive layer (28) is formed in the trench, thereby forming a top cell plate of the trench capacitor.

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B.W. Shen et al., Scalability of a Trench Capacitor Cell for 64 MBIT DRAM, 1989 IEEE, pp. 27-30.
Takeshi Hamamoto et al., Characterization of the Cell Leakage of a Stacked Trench Capacitor (STT) Cell, 1994 IEEE, pp. 1801-1805.

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