Method of forming a transistor having an offset channel section

Fishing – trapping – and vermin destroying

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437 52, 437 56, 437913, 148DIG150, H01L 21265

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active

053745728

ABSTRACT:
The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.

REFERENCES:
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patent: 5047812 (1991-09-01), Pfiester
patent: 5100816 (1992-03-01), Rodder
patent: 5155054 (1992-10-01), Itoh
patent: 5156987 (1992-10-01), Sandhu et al.
Yamanaka, et al.; "A 5.9 .mu.m2 Super Low Power SRAM Cell Using a New Phase-Shift Lithography"; IEDM; pp. 477-480 (1990).
Ikeda, et al.; "A Polysilicon Transistor Technology For Large Capacity SRAMs"; IEDM; pp. 469-472 (1990).
Huang, et al.; "New Intra-Gate-Offset High-Voltage Thin-Film Transistor With Misalignment Immunity"; Electronic Letters; vol. 25, No. 8; pp. 544-545 Apr. 1989.
Huang, et al.; "A New Implant-Through-Contact Method for Fabricating High-Voltage TFT's"; IEEE Electron Device Letters; vol. 9, No. 7 pp. 347-349 Jul. 1988.
Uemoto, et al.; "A Stacked-CMOS Cell Technology for High-Density SRAM's"; IEEE Transactions on Electron Devices; vol. 39, No. 10; pp. 2359-2363 (Oct., 1992).

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