Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2005-11-22
2009-02-03
Luu, Chuong A. (Department: 2892)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S109000, C438S666000
Reexamination Certificate
active
07485490
ABSTRACT:
Disclosed is a stacking structure of semiconductor chips and semiconductor package using it, capable of achieving an electric insulation even if a conductive wire makes contact with a lower surface of an upper semiconductor chip, while reducing a total thickness thereof and preventing damage. The stacking structure has a substrate formed with a plurality of circuit patterns; a first semiconductor chip bonded to an upper surface of the substrate and having a first plane and a second plane formed with a plurality of input/output pads; a spacer bonded to the second plane of the first semiconductor chip; a second semiconductor chip having first and second planes, the second plane being formed with a plurality of input/output pads, the first plane being provided with an insulating member so as to allow the second semiconductor chip to be bonded to the spacer, a first conductive wire for connecting the input/output pads of the first semiconductor chip to the circuit patterns of the substrate; and a second conductive wire for connecting the input/output pads of the second semiconductor chip to the circuit patterns of the substrate.
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Min Byoung Youl
Oh Kwang Seok
Park Jong Wook
Park Young Kuk
Amkor Technology Inc.
Gunnison McKay & Hodgson, L.L.P.
Hodgson Serge J.
Luu Chuong A.
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