Method of forming a stack of semiconductor packages

Details Method of forming a stack of semiconductor packages Method of forming a stack of semiconductor packages

2005-10-19

2008-12-02

Zameke, David A (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

C438S109000, C438S127000, C257SE21502, C257SE21506

Reexamination Certificate

active

07459349

ABSTRACT:
A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

REFERENCES:
Akito Yoshida et al., “Design and Stacking of An Extremely Thin Chip-Scale Package”,Electronic Components and Technology Conference, May 27-30, 2003, IEEE pp. 1095-1100.

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