Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Compound semiconductor
Reexamination Certificate
2002-04-23
2004-06-01
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Compound semiconductor
C438S047000, C438S149000, C438S235000, C438S311000, C438S312000, C438S966000, C438S967000
Reexamination Certificate
active
06743651
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor substrate, and more particularly to a method of fabricating a substantially relaxed SiGe-on-insulator substrate material by implanting oxygen into a multilayer structure which includes alternating Si and SiGe layers.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there has recently been a high-level of activity using SiGe-on-insulator materials as a substrate for strained Si-based heterostructures. As is well known, strained Si-based heterostructures achieve high mobility structures for complementary metal oxide semiconductor (CMOS) applications. In a typical prior art process, a thick strained Si layer (on the order of from about 1 to about 5 micrometers) is grown on a relaxed SiGe buffer layer. In some applications, the relaxed buffer layer is the top layer of a SiGe-on-insulator substrate material.
A typical prior art SiGe-on-insulator substrate is shown, for example, in FIG.
1
. Specifically, the SiGe-on-insulator substrate illustrated in
FIG. 1
comprises bottom Si substrate
10
, insulating, i.e., buried oxide, region
12
present atop Si substrate
10
, and relaxed SiGe layer
14
present atop insulating region
12
. In such a structure, the insulating region electrically isolates the top relaxed SiGe layer from the bottom Si substrate.
In the prior art, SiGe-on-insulator substrates may be formed utilizing one of the following three techniques: (1) wafer bonding; (2) direct implantation of Ge into a silicon-on-insulator substrate (SOI); or (3) direct implantation of oxygen into SiGe layers followed by annealing. Although the above-identified prior art methods of fabricating SiGe-on-insulators have been successfully employed in the past, each of the aforementioned prior art processes have some problems associated therewith.
For example, in fabricating a SiGe-on-insulator substrate using bonding, there are no straightforward means of thinning the SiGe-on-insulator substrate once the layer has been transferred. With silicon-on-insulators (SOIs), the top Si layer can be thinned by oxidation and subsequent oxide removal. Such a technique, however, can create rough surfaces with SiGe layers due to the SiGe snowplowing effect. The Ge concentration in the SiGe layer increases as the thinning proceeds and when the Ge concentration is too high, e.g., >25-30%, high surface roughness typically results.
Direct implantation of Ge into SOI films has an advantage over bonding in that the buried oxide region is already created before formation of the SiGe layer. However, direct implantation of Ge into Si is likely to create a very large density of defects that will compromise the crystalline quality of the resulting SiGe-on-insulator.
The third known technique for forming SiGe-on-insulator substrates is by direct oxygen implantation into SiGe layers followed by a subsequent high temperature (on the order of 1000° C. or above) annealing step. The direct oxygen implantation and annealing into SiGe layers is, however, limited to using SiGe layers that have a Ge content of less than 15 atomic percent.
In view of the drawbacks mentioned hereinabove with prior art methods of fabricating SiGe-on-insulator substrates, there is a need for providing a new and improved method for fabricating SiGe-on-insulator substrates wherein the top layer of the substrate is comprised of a substantially relaxed SiGe layer which may have a thickness of about 1000 Å or less.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a substantially relaxed SiGe-on-insulator substrate material for use in CMOS applications.
A further object of the present invention is to provide a method of fabricating a substantially relaxed SiGe-on-insulator substrate which includes SiGe layers above the buried oxide region that have a high-crystalline quality and a thickness of about 1000 Å or less.
A further object of the present invention is to provide a method of fabricating a substantially relaxed SiGe-on-insulator substrate which includes a top SiGe layer that has a low defect density (on the order of about 1×E7 defects/cm
2
or less) associated therewith.
Another object of the present invention is to provide a method of fabricating a substantially relaxed SiGe-on-insulator substrate which has a uniform composition in the insulating region and has a top SiGe layer which has a higher Ge content than that which can be obtained using prior art direct implantation of oxygen into SiGe layers.
These and other objects and advantages can be achieved in the present invention by implanting oxygen into a multilayer heterostructure that comprises alternating Si and SiGe layers. The inventive method positions the Si and SiGe layers of the multilayer structure in such a way so as to form a buried oxide layer in a region of the multilayer heterostructure containing predominately Si to facilitate the formation of a high-quality buried oxide region. Furthermore, a surface Si layer (referred to hereinafter as a Si capping layer) may be employed as a sacrificial layer for the formation of a surface oxide layer during the high-temperature annealing step needed to form the buried oxide.
In broad terms, the inventive method comprises the steps of:
implanting oxygen ions into a multilayer heterostructure comprising alternating layers of Si and SiGe, wherein said multilayer heterostructure has an uppermost layer of SiGe; and
annealing said multilayer heterostructure containing implanted oxygen ions to form a buried oxide region predominately within one of the Si layers of the multilayer heterostructure.
It is noted that the present invention contemplates the formation of patterned as well as unpatterned buried oxide regions. The term “unpatterned buried oxide region” is used herein to denote a buried oxide region that is present uniformly and continuously throughout the entire relaxed SiGe-on-insulator substrate, whereas the term “patterned buried oxide region” denotes a buried oxide region that is present as discrete and isolated islands throughout the relaxed SiGe-on-insulator substrate.
In some embodiments of the present invention, a Si capping layer may be formed atop the uppermost SiGe layer of the multilayer structure. When such an embodiment is employed, the Si capping layer serves as a sacrificial layer for the formation of a surface oxide layer that forms during the annealing step. The Si capping layer may be formed prior to, or after the implant step of the present invention.
REFERENCES:
patent: 5847419 (1998-12-01), Imai et al.
patent: 6602613 (2003-08-01), Fitzgerald
Ishikawa et al., SiGe-on-insulator substrte using SiGe alloy grown Si(001), Aug. 16, 1999, Applied Physics Letters, vol. 75, No. 7, pp. 983-985.*
Fukatsu S., SiGe-based semiconductor-on-insulator substrate created by low-energy separation-by-implanted-oxygen, Jun. 29, 1998, Applied Physics Letters, vol. 72, No 26, pp. 3485--3487.
Chu Jack O.
Huang Feng-Yi
Koester Steven J.
Sadana Devendra K.
International Business Machines - Corporation
Pham Long
Rao Shrinivas H
Scully Scott Murphy & Presser
Trepp, Esq. Robert M.
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