Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-12-13
2004-05-18
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S710000, C438S700000, C438S724000, C438S744000, C438S749000, C438S757000
Reexamination Certificate
active
06737359
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method of forming a shallow trench isolation using a silicon oxynitride anti-reflective coating which does not suffer from water spot defects.
2) Description of the Prior Art
In order to improve the photo window resolution for active areas below 0.25 microns, a silicon oxynitride anti-reflective coating can be formed on a silicon nitride layer. However, the silicon oxynitride will induce a water spot defect following a B-cleaning process (e.g. SPM+DHF+SC-
1
+SC-
2
). If the water spot defect occurs on the shallow trench isolation area, it will cause a void in the oxide reducing the yield.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,786,263 (Perera) shows a STI trench etch and fill process.
U.S. Pat. No. 5,721,174 (Peidous) discloses a SiN barrier layer and trench etch process.
U.S. Pat. No. 5,679,599 (Mehta) and U.S. Pat. No. 5,459,096 (Venkatesane et al.) show STI trench etch and barrier layer processes.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a shallow trench isolation for a device having an active area below 0.25 using a silicon oxynitride anti-reflective coating with improved yield.
It is another object of the present invention to provide a method for forming a shallow trench isolation with a silicon oxynitride anti-reflective coating which is free from water spot defects.
It is yet another object of the present invention to provide an economical method for forming a shallow trench isolation with a silicon oxynitride anti-reflective coating which has an improved yield.
To accomplish the above objectives, the present invention provides a method for forming a shallow trench isolation using a SiON anti-reflective coating which eliminates water spot defects. The method begins by providing a substrate. A pad oxide layer is formed over the substrate. A silicon nitride layer is formed on the pad oxide layer. A silicon oxynitride layer is formed on the silicon nitride layer. A photoresist mask, having an opening, is formed over the silicon oxynitride layer. The silicon oxynitride layer, the silicon nitride layer, the pad oxide layer, and the substrate are etched through the opening, forming a trench. The photoresist mask is removed. In the key step, the silicon oxynitride layer is removed using a buffered oxide etch. A thin lining oxide layer is grown. Then, a silicon oxide layer is deposited and planarized to form a shallow trench isolation.
The present invention provides considerable improvement over the prior art. The key advantage is that the process yield is improved by eliminating water spot defects.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 3657030 (1972-04-01), Porter
patent: 5459096 (1995-10-01), Venkatesan et al.
patent: 5679599 (1997-10-01), Mehta
patent: 5721174 (1998-02-01), Peidous
patent: 5786263 (1998-07-01), Perera
patent: 5949126 (1999-09-01), Dawson et al.
patent: 6001704 (1999-12-01), Cheng et al.
patent: 6020230 (2000-02-01), Wu
patent: 6051510 (2000-04-01), Fulford, Jr. et al.
patent: 6087236 (2000-07-01), Chau et al.
Chung Chaucer
Yang Shu-Yuan
Ackerman Stephen B.
Kunemund Robert
Saile George O.
Taiwan Semiconductor Manufacturing Company
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