Method of forming a shallow trench isolation structure

Details Method of forming a shallow trench isolation structure Method of forming a shallow trench isolation structure

1999-01-25

2001-05-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000

Reexamination Certificate

active

06238996

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87113896, filed Aug. 24, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of forming a shallow trench isolation structure, and more particularly to a method of avoiding stress centralized in the device active regions of fabricating the shallow trench isolation structure.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for quiet a period of time, it is one of the most reliable and low cost methods for fabricating device isolation region. However, there are still some drawbacks of the LOCOS. The drawbacks include internal stress generation and bird's beak encroachment. For a high-integrated device, the problem of bird's beak encroachment by isolation regions is especially difficult to avoid, thus the isolation regions cannot effectively isolate devices.
Shallow trench isolation (STI) technique is the other conventional method of forming isolation regions. Shallow trench isolation is formed by first anisotropically etching to form a trench in the substrate, and then depositing oxide in the trench to form an isolation region. Since shallow trench isolation is scaleable and has no bird's break encroachment problem found in the conventional LOCOS technique, it become widely used for forming sub-micron CMOS circuits.
There are still some problems in the prior art of forming a shallow trench isolation structure, and these problems will be described in detail in accordance with
FIGS. 1A-1B
, which are schematics, cross-sectional views illustrating the formation of a shallow trench isolation structure in accordance with the prior art.
In
FIGS. 1A
, a pad oxide layer
102
and a silicon nitride mask layer
104
is formed on the substrate
100
. A trench
106
is formed in the substrate
100
by removing portions of the silicon nitride layer
104
, the pad oxide layer
102
, and the substrate
100
. Then, a liner oxide
108
is formed on the surface of the trench
106
in the substrate
100
, and an insulating layer
110
is formed over the silicon substrate
100
to fill the trench
106
by atmospheric pressure chemical vapor deposition (APCVD). A densification step is performed at a high temperature to make the silicon oxide insulating layer
110
compact.
In
FIG. 1B
, chemical-mechanical polishing is performed while using the silicon nitride mask layer
104
as polishing stop layer to remove the excess insulating layer
110
. Hot phosphoric acid solution is used to remove the silicon nitride mask layer
104
and to expose the pad oxide layer
102
. An isolation region
112
is formed in the substrate
100
after the pad oxide layer
102
is removed with HF solution.
The angle between the sidewall and the bottom surface of the trench
106
is an obtuse angle, which means that the angle of the bottom corner
130
is larger than 90 degrees and smaller than 180 degrees. Stress is created in the bottom corner
130
of the trench
106
when the liner oxide layer
108
is formed and easily centralized in the device active regions
120
(shown in
FIG. 1B
) along the sidewall of the trench
106
because of the obtuse geometry of the bottom corner
130
in the trench
106
.
During the densification step, since the crystal structure of the silicon substrate
100
experiences excessive compression or tension, the stress created while forming the liner oxide layer
108
is released to the single crystal structure substrate
100
to cause dislocations, which is one of the most common line defects. In addition to the high temperature densification step, dislocations are also created in the single crystal structure of silicon substrate
100
during the subsequent steps of forming source/drain regions. When dislocations extend to the source/drain regions, the dopants in the source/drain regions diffuse along the defect direction, and leakage current and/or punch through are created and the conductivity of devises is reduced. This phenomena becomes worse as the downsizing of devices and shortening of distance between devices, furthermore, it makes the device failure occur and lower the production yield.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved method of forming a shallow trench isolation structure to avoid stress centralization to solve the problems occur in the prior art, so as to prevent the dysfunction of devices.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of forming a shallow trench isolation structure. A concave trench is formed in a single crystal substrate with a defined mask layer. The surface of the concave trench is smooth and without any sharp turning points. The concave trench is filled with insulating materials, and the mask layer is removed until the substrate is exposed, and a shallow trench isolation structure with a concave trench is formed.
A shallow trench isolation structure of a trench with concave bottom corners is disclosed in this invention, too. The surfaces of the concave bottom corners in the trench are smooth and without any sharp turning points. The shallow trench isolation structure is finished after the trench filled with insulating materials and the mask layer being removed.
Stress centralization is prevented by the structure of concave trench and a trench with concave bottom corners formed according to the methods of the first and the second preferred embodiments of this invention. The concave trench and the trench with concave bottom corners also avoid the creation of leakage current and/or the punch through phenomenon in the source/drain regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5801082 (1998-09-01), Tseng
patent: 6057208 (2000-05-01), Lin et al.
patent: 6060370 (2000-05-01), Hsia et al.
patent: 6071792 (2000-06-01), Kim et al.
patent: 6107159 (2000-08-01), Chuang

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