Method of forming a semiconductor device package using a...

Details Method of forming a semiconductor device package using a... Method of forming a semiconductor device package using a...

2002-06-12

2004-08-24

Chambliss, Alonzo (Department: 2827)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S613000, C029S874000

Reexamination Certificate

active

06780673

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device package structure and method of forming contact pads for a packaged semiconductor device.
BACKGROUND
Integrated circuit devices typically include a semiconductor chip that is assembled in a package. Many types of packages exist. One such package configuration is a flip-chip ball grid array.
FIGS. 1-6
illustrate the steps for forming a typical flip-chip ball grid array for a semiconductor device package.
FIG. 1
shows a cross-section view of a package substrate
34
for use in assembling a packaged semiconductor device. Note that the terms “semiconductor device” and “integrated circuit device” may be used interchangeably herein. Note also that the term “chip” may be interchanged with the term “die.” The package substrate
34
has multiple layers
35
laminated together with vias
36
and traces
38
routed therethrough. The layers
35
of the package substrate
34
may be made from organic materials and/or fiberglass, for example. In
FIG. 2
, a layer of copper
40
is formed on the top layer
42
of the package substrate
34
.
FIG. 3
shows a group of copper contact pads
44
formed from the copper layer
40
. Between
FIGS. 2 and 3
are conventional process steps not shown, which may include: applying a resist layer, exposing the resist layer through a mask, developing the resist layer, forming a pattern in the resist from the mask image, etching the copper layer in the pattern formed in the resist, and striping the remaining resist. One of ordinary skill in the art will be familiar with the conventional process steps to get from
FIG. 2
to FIG.
3
.
In
FIG. 4
, a layer of organic material
46
is applied on the top layer
42
of the package substrate over the contact pads
44
.
FIG. 5
shows a solder mask
46
formed from the organic material layer. Between
FIGS. 4 and 5
are conventional process steps not shown, as discussed above, which one of ordinary skill in the art will be familiar with. The solder mask
46
is typically at least about 5-30 microns taller than the contact pads
44
. In
FIG. 6
, a chip
52
having solder balls
50
deposited thereon is mated with the contact pads
44
and the solder balls
50
are soldered (e.g., by reflowing the solder) to the contact pads
44
. The solder mask
46
is intended to prevent solder of the solder balls
50
from bonding to the top layer
42
of the package substrate
34
and/or flowing across to an adjacent solder ball
50
.
FIG. 7
shows a chip
52
attached to the package substrate
34
via the solder balls
50
to form a packaged integrated circuit device
30
. After the chip
52
is attached to the package substrate
34
, an underfill material
54
is injected into the space between the chip
52
and the package substrate
34
, as well as between and around the solder balls
50
. After the underfill material
54
is injected as a liquid, it is then cured to form a solid layer. One of the purposes of the underfill layer
54
is form a composite of the chip
52
and package substrate
34
, to mechanically couple the chip
52
to the package substrate
34
, and to relieve stresses that would otherwise be exerted on the solder balls
50
. The difference in the thermal expansion rates for the chip
52
and the package substrate
34
are often quite different, which may cause stress on the solder joints at the solder balls
50
as temperatures vary. Hence, some of the thermal stress can be transferred to the underfill layer
54
to relieve stress on solder joints and solder balls
50
. The underfill material
54
may be epoxy, anhydride, a silicon compound, or any combination thereof, for example.
Due at least in part to the process of forming the underfill layer
54
and/or due to gas bubbles in the underfill layer
54
, the underfill layer
54
typically has voids or cavities formed therein. Such voids or cavities are sources of stress concentration and may lead to the development of a crack in the underfill layer
54
. The underfill material
54
is usually more brittle than that of the solder balls
50
. When a crack initiates, the crack creates another location for stress concentration to arise and the crack will often have a tendency to propagate until the stress concentration is relieved. A crack
56
is shown in
FIG. 7
to illustrate an example of how a crack
56
initiated in the underfill layer
54
may propagate through the solder mask
46
and into the package substrate
34
. In the case of
FIG. 7
, the crack
56
has propagated through a via
36
, which may cause an “open” or an electrical discontinuity at the via
36
. With the current structure shown in
FIG. 7
, a crack
56
that develops in the underfill layer
54
will often propagate through the solder mask
46
and into the package substrate
34
because the solder mask
46
and the package substrate
34
are typically made from similar materials, such as organic materials for example, and/or they have similar material properties. Hence, there is a need for an improved structure for a package substrate
34
that can reduce or hinder the propagation of cracks
56
initiated in the underfill layer
54
.
BRIEF SUMMARY OF THE INVENTION
The problems and needs outlined above are addressed by certain aspects of the present invention. In accordance with one aspect of the present invention, a method of forming a package for an integrated circuit device is provided. The method includes the following steps, the order of which may vary: contact pads are formed on a top layer of a package substrate and a plate layer is formed on the top layer of the package substrate. The plate layer is located in an area outside of the contact pads, and the plate layer has a thickness about equal to a thickness of the contact pads.
In accordance with another aspect of the present invention, a method of forming a package for an integrated circuit device is provided. This method includes the following steps, the order of which may vary: a layer of conductive material is formed on a top layer of a package substrate, and a portion of the conductive material layer is removed to form channels. Each channel defines a corresponding contact pad surrounded by the channel. Each contact pad is formed from the conductive material layer. Each channel is surrounded by a remaining portion of the conductive material layer outside of the channel. An oxide layer, for example, may be formed over the contact pads, the channels, and the remaining portion of the conductive material layer, and portions of the oxide layer may be removed from the contact pads to expose the contact pads. Solder balls may be deposited on each of at least some of the contact pads, and the oxide layer may hinder the solder balls from bonding to the remaining portion of the conductive material layer surrounding the channels with the oxide layer. In alternative, an organic material layer may be used, for example, instead of or in addition to an oxide layer. A chip may be soldered to the solder balls, such that the solder balls are sandwiched between the chip and the substrate, and such that the contact pads are electrically coupled to the chip via the solder balls. An underfill material may be injected between the package substrate and the chip, as well as substantially around the solder balls. When cured, the underfill material may form an underfill material layer between the chip and the package substrate with the solder balls embedded therein.
In accordance with yet another aspect of the present invention, a semiconductor device is provided, which includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The layer of conductive material is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact

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