Method of forming a semiconductor device having a vertical insul

Details Method of forming a semiconductor device having a vertical insul Method of forming a semiconductor device having a vertical insul

1995-06-06

1996-06-18

Thomas, Tom

Fishing, trapping, and vermin destroying

H01L 218232

Patent

active

055277209

ABSTRACT:
A semiconductor device (1) includes a vertical insulated gate field effect device (2) and has a semiconductor body (3) with a first semiconductor region (4) of one conductivity type adjacent one major surface (5). A second semiconductor region (6) of the opposite conductivity type is formed within the first region (4) adjacent the surface (5) and a third region (7) forms with the second region (6) a rectifying junction (8) meeting the one major surface (5). A recess (9) extends into the first region (4) from the one major surface (5) so that the second and third regions (6 and 7) abut the recess (9), and an insulated gate (10) is formed within the recess (9) for controlling conduction between the first and third regions (4 and 7) along a conduction channel area (61) of the second region (6). A fourth region (11) of the one conductivity type forms with a portion (6b) of the second region (6) of the opposite conductivity type remote from the recess (9) a further rectifying junction (12) which is reverse-biassed in at least one mode of operation of the device and has a predetermined breakdown voltage for causing the device to breakdown in the vicinity of the further rectifying junction (12) away from the recess (9) when a critical voltage is exceeded.

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