Method of forming a semiconductor device

Details Method of forming a semiconductor device Method of forming a semiconductor device

1998-06-03

2001-05-15

Gulakowski, Randy (Department: 1746)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S623000, C438S736000

Reexamination Certificate

active

06232235

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and in particular, to forming low dielectric constant interlevel dielectric layers for those devices.
BACKGROUND OF THE INVENTION
Semiconductor devices are continuing to being scaled to smaller dimensions. Copper interconnects and low dielectric constant (low-k) materials are two areas of technology that are being developed by semiconductor device manufacturers in an effort to reduce device dimensions. A film's dielectric constant is a measure of its electrical insulating value. Air has a dielectric constant, or k value equal to one. Commonly used silicon dioxide (SiO
2
), by comparison, has a dielectric constant of approximately 4.0. For the purposes of this specification, a low-k material is any material having a dielectric constant less than approximately 3.5.
In one particular interconnect scheme, a dual inlaid structure is formed. After forming a first interconnect level, an interlevel dielectric (ILD) layer having a dual inlaid opening is formed. One prior art technique uses three relatively high dielectric constant hardmask films with low-k dielectric films layered between them. The dual inlaid structure is formed by opening a via and a trench in the dielectric films using a “via first, trench last” or “trench first, via last” processing sequence. Following these steps, an interconnect structure is formed within the trench and the via opening.
One problem with the prior art includes its use of chemically vapor deposited silicon nitride materials including plasma enhanced silicon nitride or silicon oxynitride compounds to form the hardmask. These materials have a relatively high dielectric constant (i.e., greater than five) that increases the total dielectric constant of the ILD layer and raises the total capacitance within the structure. Another problem with the prior art is that the top hardmask film is susceptible to erosion when forming the trench and the via openings. If the hardmask is eroded to a point where the underlying low-k dielectric is exposed during the trench or via etch, the low-k dielectric film will begin to etch laterally resulting in wider than specified feature sizes.


REFERENCES:
patent: 5565384 (1996-10-01), Havemann
patent: 5597764 (1997-01-01), Koh et al.
patent: 5646440 (1997-07-01), Hasegawa
patent: 5679608 (1997-10-01), Cheung et al.
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5920790 (1999-07-01), Wetzel et al.
U.S. application No. 08/868,332, Wetzel, filed Jun. 2, 1997.

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