Method of forming a self-aligned trench isolation

Details Method of forming a self-aligned trench isolation Method of forming a self-aligned trench isolation

2000-10-25

2001-07-24

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257S374000, C438S296000

Reexamination Certificate

active

06265285

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the manufacture of a trench isolation in a semiconductor device, and more particularly, to a method of forming a trench isolation for a semiconductor device in combination with a poly-oxide spacer process and a self-aligned trench process.
BACKGROUND OF THE INVENTION
The trench isolation structure and process is important for the manufacture of a semiconductor device to isolate microelectronic devices in the semiconductor device. For the microelectronic devices to be placed increasing closer to each other without causing detrimental electronic interaction such as unwanted capacitance build-up and current leakage, advanced trench isolation structure and process is desired.
In a conventional trench isolation, an isolation trench is formed in a semiconductor substrate and then filled up with an isolation material, and the active area of the semiconductor substrate is covered with a pad oxide thereon. However, the isolation material in the isolation trench exhibits a non-planarity at the top surface thereof between corners due to dissimilarity of etch rates between the isolation material and pad oxide. A problem that is inherent in such non-planarity of fill material within an isolation trench is that the corners may leave the active area of the semiconductor substrate exposed. As a result, the isolation material will not prevent layers formed thereon contacting the active area of the semiconductor substrate at the corners, which is detrimental in that it causes charge and current leakage. The isolation material is also unable to prevent unwanted thermal oxide encroachment through the corners into the active area of the semiconductor substrate.
Gonzalez et al. disclose a self-aligned isolation trench and a method of forming such an isolation trench structure without causing deleterious topographical depressions in upper surface thereof which cause current and charge leakage to an adjacent active area, respectively in U.S. Pat. Nos. 6,097,076 and 5,953,621. These prior arts form a nitride layer on the pad oxide which is grown upon a semiconductor substrate. After patterning the nitride layer to expose a portion of the pad oxide layer, a second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of a first dielectric layers. A spacer is formed from the second dielectric layer, and then an isolation trench is etched into the semiconductor substrate. A conformal layer is formed substantially conformably over the spacer and the remaining portions of the first dielectric layer, and substantially filling in the isolation trench. After planarization of the conformal layer, the resulting structure has a flange and shaft, the cross section of which has a nail shape in its cross section.
However, even though Gonzalez et al. improve the trench isolation by the above-described arts, the method of forming the isolation trench is still complicated. It is therefore desired a further improvement for the trench isolation process over the method provided by Gonzalez et al.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of forming a trench isolation on a semiconductor substrate without causing deleterious topographical depressions in the upper surface of the fill dielectric material in the isolation trench, while substantially preventing contact between the layers overlying the fill dielectric material of the isolation trench and the active area of the semiconductor substrate.
According to the present invention, a method of forming a trench isolation comprises depositing a silicon film upon a pad oxide that covers on a semiconductor substrate and then patterning the silicon film to expose the pad oxide and form a first opening. The silicon film is substantially thermally oxidized to form a poly-oxide layer on its surface, and a second opening is thus formed between the poly-oxides on the sidewalls of the silicon film. A directional etch is applied to the poly-oxide layer and pad oxide to form a poly-oxide spacer and expose the semiconductor substrate. A plasma etch is used through the second opening to form an isolation trench in the semiconductor substrate. A dielectric film is deposited and fills in the isolation trench. The portions of the dielectric film covered on the top planar portions of the silicon film is substantially removed to expose the silicon film by a chemical mechanical polishing (CMP) process. Then the silicon film is removed to leave a trench isolation structure with a nail shape in its cross section on the semiconductor substrate.
Thus the process of forming a trench isolation on a semiconductor substrate becomes simpler and the width of the isolation trench can be made narrower.


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Takeuchi et al., A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories, Dig. of Tech. Papers Symp. on VLSI Tech, Jun. 1998, pp. 102-103.

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