Method of forming a self-aligned low density drain inverted thin

Details Method of forming a self-aligned low density drain inverted thin Method of forming a self-aligned low density drain inverted thin

1993-07-15

1995-01-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437913, H01L 21265

Patent

active

053858549

ABSTRACT:
A process for forming a thin film transistor having a lightly doped drain which is self-aligned with the transistor channel. A transistor gate is formed over a first dielectric layer, and a second dielectric layer is formed over the transistor gate. A layer of polycrystalline silicon (poly) is formed over said second dielectric layer, and the poly layer can be optionally doped with a P-type or N-type dopant to adjust the threshold voltage of the transistor. Next, an implant masking layer is formed over the gate, and has an etch mask thereupon. The exposed implant masking layer is removed, and in one embodiment the etch mask is undercut during the same etch to remove portions of the implant masking layer from under the etch mask. The exposed poly is doped with a P-type dopant. The etch mask is removed and the exposed poly is again doped with a P-type dopant to form the lightly doped drain using the implant mask to self-align the lightly doped drain with the channel region. Other embodiments include the formation of an N-type metal oxide semiconductor and a separate undercut etch.

REFERENCES:
patent: 4372033 (1983-02-01), Chiao
patent: 4393578 (1983-07-01), Cady et al.
patent: 4417385 (1983-11-01), Temple
patent: 4933994 (1990-06-01), Orban
patent: 5151374 (1992-09-01), Wu
patent: 5198379 (1993-03-01), Adan
patent: 5214295 (1993-05-01), Manning

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