Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-12-20
2002-08-13
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S729000
Reexamination Certificate
active
06432833
ABSTRACT:
TECHNICAL FIELD
The invention relates to methods of forming self-aligned contact openings.
BACKGROUND OF THE INVENTION
Yield in the semiconductor fabrication industry is a measure of the percentage of operable chips produced in the fabrication of circuitry on a semiconductor wafer. Semiconductor fabricators are ever attempting to increase yield, and are sensitive to anything that decreases yield.
One aspect in semiconductor circuitry fabrication impacting yield is the plasma etching which is conducted to form self-aligned contact openings to substrate active area. Such etching is typically conducted through a doped silicon dioxide layer formed over active area and transistor gates which have their sides and tops covered with an insulating material other than doped silicon dioxide, for example silicon nitride. Plasma etching can be conducted which is substantially selective to silicon nitride and underlying silicon of the active areas, thereby being self-aligning with respect to a silicon nitride covered gate.
However, mask opening size or misalignment might result in the contact opening overlying a substrate isolation region which typically borders the active areas. These are commonly comprised of undoped silicon dioxide. It is problematic to achieve acceptable selectivity in etching doped silicon dioxide selectively relative to undoped silicon dioxide of the isolation regions. The literature supposedly reports several processes capable of achieving reasonably selective etches in such instances, yet satisfactory results are not always achieved which ultimately adversely affects yield. Undesired etching into the isolation oxide can adversely affect the circuitry, and thus destroy the product being produced where a contact opening inadvertently or desirably overlaps a substrate isolation region comprised principally of undoped silicon dioxide.
Accordingly, a need remains for improved methods of forming self-aligned contact openings to active areas where transistor gates are overlapped and substrate isolation regions of undoped oxide may or may not be exposed during the etch.
SUMMARY
The invention comprises a method of forming a self aligned contact opening. In one implementation, a bulk semiconductor substrate is provided which has an active area received between at least two undoped silicon dioxide comprising substrate isolation regions. The substrate has at least two transistor gate constructions received at least partially over the active area. The gate constructions include gates having their sides and tops covered with insulating material comprising at least one of undoped silicon dioxide and silicon nitride. A doped silicon dioxide layer is formed over the active area, the isolation regions and the gate constructions. A patterned masking layer is formed over the doped silicon dioxide layer. The patterned masking layer has a mask opening formed therein which overlaps at least one of the gate constructions and the active area. The substrate is placed within a high density plasma etcher. The etcher has a top power electrode and a biasable electrostatic chuck. Plasma etching is conducted through the mask opening, using a hydrogen containing fluorocarbon chemistry, a top electrode power less than or equal to 1000 W per 200 mm of substrate diameter, and an electrostatic chuck bias power less than the top electrode power by no more than 300 W, into the doped oxide substantially selective to the active area, insulating material and any overlapped area of the substrate isolation regions to form a substantially self aligned contact opening to the active area.
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Chen Kin-Chan
Utech Benjamin L.
Wells St. John P.S.
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