Method of forming a self-aligned bipolar transistor using amorph

Details Method of forming a self-aligned bipolar transistor using amorph Method of forming a self-aligned bipolar transistor using amorph

1989-06-23

1990-12-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437162, 437192, 437193, 437200, 437202, 437247, 148DIG1, 148DIG147, H01L 21265, H01L 21283

Patent

active

049770985

ABSTRACT:
A process for manufacturing a polysilicon-based bipolar semiconductor device, in particular an improved emitter contact configuration, eliminates native oxide anomalies at semiconductor interface regions, thus improving the characteristics of the emitter and its associated contact. Unwanted oxide is sputtered off the surface of a silicon substrate, so as to provide an effectively clean substrate surface. Next, a first amorphous silicon layer is formed on the surface of the substrate. Dopants are then implanted into the first amorphous silicon layer, to provide a source of diffusion impurities for forming an underlying (emitter) region. The resulting structure is then subjected to a rapid anneal which causes the impurities within the first amorphous silicon layer to diffuse into the substrate, forming the emitter region. Unwanted oxide that has been formed on the surface of the first amorphous silicon layer during the diffusion step is removed by sputtering. A titanium film and an overlying second amorphous silicon layer (ion-implanted with impurities) are formed atop the first amorphous silicon layer and the resulting structure is subjected to a further rapid anneal, so as to form a titanium-silicide layer that is intermediate and contiguous with the first and second amorphous layers.

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Horng, "Self-Aligned Process for Providing an Improved High Performance Bipolar Transistor", U.S. Defensive Publication, No. T104,803, Nov. 6, 1984.

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