Method of forming a resistor for ESD protection in a self aligne

Details Method of forming a resistor for ESD protection in a self aligne Method of forming a resistor for ESD protection in a self aligne

1996-03-06

1996-08-20

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437200, 437918, H01L 21266

Patent

active

055478816

ABSTRACT:
A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The high resistance contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation at the high resistance contact region into the metal which will be used to form the metal silicide low resistance contacts converts the metal at the high resistance contact region to metal nitride. Since all the metal at the high resistance contact region is converted to metal nitride there is no free metal to form metal silicide at the high resistance contact region when the low resistance metal silicide contacts are formed. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.

REFERENCES:
patent: 4370798 (1983-02-01), Lien et al.
patent: 4859278 (1989-08-01), Choi
patent: 4959329 (1990-09-01), Okamoto et al.
patent: 5508212 (1996-04-01), Wang et al.
VLSI Technology-2nd Edition by S. M. Sze, McGraw Hill Book Co., Singapore, 1988, pp. 368-369.
"Silicon Processing For The VLSI Era-Vol. 1" Lattice Press, Sunset Beach, CA, 1986, pp. 390-391.

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