Method of forming a novel vertical-gate CMOS compatible lateral

Details Method of forming a novel vertical-gate CMOS compatible lateral Method of forming a novel vertical-gate CMOS compatible lateral

1994-02-28

1994-12-06

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 84, 437243, H01L 21265

Patent

active

053710223

ABSTRACT:
A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

REFERENCES:
patent: 5102809 (1992-04-01), Eklund et al.
patent: 5164326 (1992-11-01), Foerstrer et al.
patent: 5273915 (1993-12-01), Hwong et al.
patent: 5316957 (1994-05-01), Spratt et al.
B. S. Meyerson; "Low-Temperature Silicon Epitaxy by Ultrahigh Vacuum/Chemical Vapor Deposition"; Appl. Phys. Lett. 48 (12); 24 Mar. 1986, pp. 797-799.
L. Jastrzebski; "SOI by CVD: Epitaxial Lateral Overgrowth (ELO) Process-Review"; Journal of Crystal Growth 63 (1983); pp. 493-526.

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