Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor...
Reexamination Certificate
1999-07-22
2001-04-24
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
C438S156000, C438S158000, C438S173000, C438S175000, C438S268000, C438S270000, C438S282000, C257S051000, C257S066000, C257S328000, C257S329000, C257S330000
Reexamination Certificate
active
06222201
ABSTRACT:
FIELD OF INVENTION
The present invention relates to semiconductor devices, and more specifically, to a method of manufacturing of a thin film transistor with self-aligned offset and the structure of the same.
BACKGROUND
Thin film transistor (TFT) is a kind of a field effect transistor (FET). In typical FET, the source and drain and the channel region are formed in the substrate composed of single crystal silicon. The channel region of the TFT is different from the conventional FET. Namely, the channel region of the TFT is formed in a polysilicon or amorphous silicon layer on a substrate. For the application, the TFT can region of the TFT is formed in a polysilicon or amorphous silicon layer on a substrate. For the application, the TFT can be used in flat panel display as switching transistors and in static random access memory as load devices. By varying the transverse electrical field, it is possible to control the current flow by modulating the conductance of the channel. If the drain bias is applied such that source and drain remain reverse-bias. A positive bias is applied to the gate of the NMOS, electrons will be attracted to the channel region, once enough electrons are drawn into the channel region by the positive gate voltage, and the channel connects the source and the drain.
One of the key parameters to determine the performance of the device is the drain off-set structure. The off-set structure is parts outside the gate electrode. The function of the off-set structure is similar to the lightly doped drain (LDD) structure in FET. The drain off-set structure can reduce the short channel effect or reduce punch-through effect caused by hot carrier and the structure also reduces the off-state leakage. Apparently, one way to form a quality SRAM is to decrease the on off-current and increase the on-current.
FIG. 11
shows a cross sectional view of a conventional polysilicon PMOS cell. In the cell, isolation structures composed of oxide
4
a
are formed in the substrate
2
a
for isolation. A driver NMOS is formed on the top of the substrate
2
a
. A transistor
8
a is located adjacent to the NMOS. A gate
10
a
isolated by dielectric material
6
a
is formed on the driver NMOS, and a polysilicon layer
10
a
is used to connect the driver NMOS and the doped region of the transistor
8
a
. The gate
10
a
and the polysilicon layer
10
a
are composed of N type polysilicon. A P conductive type polysilicon layer
12
a
goes over the dielectric layer
6
a.
A part of the layer
12
a
is implanted to define the source and drain. An off-set can be found adjacent to the drain. The separation between the source and drain defines the channel. The channel is oriented in a direction substantially parallel to the substrate, this leads to the conventional structure occupies a large cell area. It is not suitable to the trend of manufacture with high packing density. The channel formed of polysilicon provides smaller on-current compared to monocrystalline silicon channel.
One of the approaches for the off- set structure is disclosed in U.S. Pat. No. 5,001,540 to Ishihara, he develops a dual gate TFT with off-set structure. The off-set region is the extension of a layer used to form the channel region. The dopant concentration is the same with that of channel region. Further, in the structure, the dimension of the off-set is determined by the width of the side walls spacers. Shepard provides a vertical dual gate thin film transistor, the article can be seen in U.S. Pat. No. 5,574,294. Shepard disclosed a self-aligned process for forming the source and drain regions in a dual gate TFT and further allows for the formation of off-set. Recently, some researches and developments have been approached to develop a vertical thin film transistor. The channel of the device is vertical to the surface of the substrate. Some arts provide a device cell with source, channel and drain that are vertically formed in a trench. The devices provide an advantage of higher density than others.
SUMMARY
An object of the present invention is to provide a thin film transistor (TFT) with a self-aligned offset structure.
A first polysilicon layer is deposited by chemical vapor deposition (CVD) on the substrate. Then, the doped polysilicon layer is patterned on the substrate. Side wall spacers are created on the side walls of the previous polysilicon pattern.
A first dielectric having a first via hole is defined over the substrate. The first dielectric layer can be formed of oxide layer by using a chemical vapor deposition process, with a tetraethylorthosilicate (TEOS) source, at a temperature between about 600 to 800 degrees centigrade. A second doped polysilicon layer is formed along the surface of the first dielectric layer. The doped polysilicon layer is also refilled into the first via hole and then performing an etching process to etch the polysilicon layer. A residual portion of the layer is located at the lower portion of the first via hole. An off-set structure can be controlled easily by etching time mode. An undoped polysilicon is then patterned on the first dielectric layer and along the surface of the first via hole. An isolation structure is then refilled into the first via hole. An oxide layer is formed on the first polysilicon, the first dielectric layer and the upper surface of isolation structure to act as the gate oxide of the TFT. Thus, the gate oxide is preferably formed by a so-called high temperature oxide (HTO) procedure. Then, the HTO oxide and the first dielectric layer are etched to define a second via hole.
A further doped polysilicon layer is pattern on the first dielectric layer and refilled into the second via hole for defining the control gate. Then, using the control gate pattern as a mask, an ion implantation is employed to dope conductive species into the undoped polysilicon layer uncovered by the gate structure, thereby forming the doped region to act as source or drain. An isolation layer is deposited and a third via hole is generated in the isolation layer. A further polysilicon is then patterned on the second dielectric layer.
The vertical thin film transistor includes a conductive structure formed on the substrate. A first isolation layer is formed on the conductive structure and the substrate. The first isolation layer includes an opening formed therein. A first doped region (drain or source) is located at the lower portion of the opening. A channel region is formed along at least one of the side-wall of the opening and extends outside the opening to a portion of the upper surface of the dielectric layer. An isolation structure fills in the opening. Gate oxide is formed on the channel region. A gate is patterned on the undoped polysilicon and adjacent to the opening. A second doped region is formed adjacent to the channel region connected to the channel region. A second opening is formed in the first dielectric layer adjacent to the TFT to expose the conductive structure. A conductive structure is formed in the second opening. A second dielectric layer having a third opening is formed on the TFT and the conductive structure. A third conductive structure is formed on the second dielectric layer and in the third opening.
REFERENCES:
patent: 5001540 (1991-03-01), Ishihara
patent: 5391505 (1995-02-01), Kapoor
patent: 5403761 (1995-04-01), Rha
patent: 5459088 (1995-10-01), Rha et al.
patent: 5521117 (1996-05-01), Kapoor
patent: 5523600 (1996-06-01), Kapoor
patent: 5574294 (1996-11-01), Shepard
patent: 5668391 (1997-09-01), Kim et al.
patent: 5937283 (1999-08-01), Lee
patent: 5952677 (1999-09-01), Park
patent: 6008505 (1999-12-01), Cho
patent: 6033941 (2000-03-01), Yang
patent: 6107660 (2000-08-01), Yang et al.
Liu Chia-Chen
Yang Ching-Nan
Diaz José R.
Lee Eddie C.
Worldwide Semiconductor Manufacturing Corp.
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