Method of forming a non-volatile DRAM cell

Details Method of forming a non-volatile DRAM cell Method of forming a non-volatile DRAM cell

1994-05-10

1995-02-14

Thomas, Tom

Fishing, trapping, and vermin destroying

437 43, 437 48, H01L 2170

Patent

active

053895673

ABSTRACT:
The present invention is directed to a one-transistor non-volatile DRAM cell having a two layer floating gate to allow the contents of a storage capacitor to be transferred to the floating gate during power interruptions. The first layer of the floating gate is separated from a storage node of the storage capacitor by a tunnel oxide to allow electron tunnelling between the floating gate and the storage capacitor. In another embodiment of the present invention, a dual electron injector structure is disposed between a one layer floating and the storage node to allow electrons to be injected between the floating gate and the storage node. In another embodiment of the present invention, an erase gate is implemented to remove the charge on the floating gate. The erase gate can be separated from the floating gate by a tunnel oxide or a single electron injector structure to allow electrons to travel from the floating gate to the erase gate.

REFERENCES:
patent: 4363110 (1982-12-01), Kalter et al.
patent: 4388704 (1983-06-01), Bertin et al.
patent: 4471471 (1984-09-01), DiMaria
patent: 5065201 (1991-11-01), Yamauchi
patent: 5140551 (1992-08-01), Chiu

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