Method of forming a nano-rugged silicon-containing layer

Details Method of forming a nano-rugged silicon-containing layer Method of forming a nano-rugged silicon-containing layer

1998-03-13

2000-03-21

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438255, H01L 2120

Patent

active

06040230&

ABSTRACT:
An embodiment of the instant invention is a method of forming a nano-rugged silicon-containing layer, the method comprising the steps of: providing a first silicon-containing layer (steps 202 or 802); providing a patterning layer over the first silicon-containing layer (steps 204 or 804); the patterning layer comprised of an amorphous substance; providing a second silicon-containing layer (steps 206 or 808) over the patterning layer; and wherein the patterning layer creates a nano-rugged texture in the second silicon-containing layer. Preferably, the first and second silicon-containing layers are comprised of polycrystalline silicon. In an alternative embodiment, the patterning layer is comprised of a material which has small holes such that the step of providing the second silicon-containing layer utilizes the first silicon-containing layer as a seed layer through the small holes so as to form the second silicon-containing layer. In another alternative embodiment, the second silicon-containing layer is comprised of a plurality of islands of the silicon-containing material separated by voids in the material. Preferably, the patterning layer is comprised of SiO.sub.2.

REFERENCES:
patent: 4549926 (1985-10-01), Corboy, Jr. et al.
patent: 5234857 (1993-08-01), Kim et al.
patent: 5612558 (1997-03-01), Harshfield

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