Method of forming a multi-level interconnect structure by...

Details Method of forming a multi-level interconnect structure by... Method of forming a multi-level interconnect structure by...

2011-08-16

2011-08-16

Pham, Thanh V (Department: 2894)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S975000, C438S123000, C438S458000, C257SE21540

Reexamination Certificate

active

07998827

ABSTRACT:
A method of manufacturing a semiconductor device, includes forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area, and aligning a third layer provided above the structure by using the second alignment mark.

REFERENCES:
patent: 6087733 (2000-07-01), Maxim et al.
patent: 6690045 (2004-02-01), Shinkawata
patent: 7042099 (2006-05-01), Kurashima et al.
patent: 7288848 (2007-10-01), Lee et al.
patent: 2006/0281019 (2006-12-01), Yang
patent: 2007/0222960 (2007-09-01), Van Der Schaar et al.
patent: 2004-79732 (2004-03-01), None

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