Fishing – trapping – and vermin destroying
Patent
1990-02-01
1994-11-08
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437113, 148DIG158, 20419225, H01L 2120
Patent
active
053626729
DESCRIPTION:
BRIEF SUMMARY
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates to a method to manufacture a semiconductor device, and particularly to a technique to form a thin film semiconductor element on a substrate.
In the past, various techniques have been developed to form a crystal layer of semiconductor on the insulating substrate and to form various types of devices on it. Particularly, the technique to form monocrystal silicon layer on the insulator substrate and to form a semiconductor device on it to produce the integrated circuit is called SOI (Silicon on Insulator), and fervent research and development have been performed for it. If SOI technique can be actualized, it is not only advantageous for the production of the high-speed ICs, but it will open the road toward the latch-up free CMOS circuit or toward a dynamic memory with very high soft error tolerance. Also, it may be possible to achieve IC of 3-dimensional structure by sequentially stacking up the semiconductor elements through the insulating layer on the semiconductor element.
Further, if monocrystal silicon layer can be built up at low cost on the glass substrate with large area by SOI technique, it is possible to provide a high-performance large-size flat panel type display unit. This will bring forth radical innovation to the display devices such as the wall-hanging type television set. Despite of such great expectations, SOI technique is still far from the practical application, and the development of the products based on such technique may not be actualized in near future.
In the following, the problems will be described by giving some examples on SOI technique.
SOS (Silicon on Sapphire) technique is a technique known since many years. This is a technique to form Si thin film on sapphire (A1.sub.2 O.sub.3) by epitaxial growth and to form IC. Despite of practical application and commercial production since many years, this did not constitute the main stream of SOI technique and is applied only in limited application fields because the product cost of sapphire substrate is higher than silicon wafer and because crystal defect occurs due to the difference of lattice constants of crystal between sapphire and silicon and it is difficult to produce a high-performance device.
In contrast, new techniques have emerged in these 10 years, by which monocrystal silicon thin film is formed on the insulator substrate surface with no crystal property such as SIO.sub.2, Si.sub.3 N.sub.4, AlN, etc. The technique of grapho-epitaxy is one of such new techniques. As shown in FIG. 12, grooves are formed periodically on the surface of SIO.sub.2 substrate 1201, and amorphous silicon 1202 silicon 1202 is stacked on it. Then, laser beam is applied by scanning the substrate to produce a partially melted region 1203, and silicon is turned to monocrystal by it. Once silicon is melted, the grating pattern is formed on the surface of the substrate during recrystallization. The crystals aligned to the direction of this pattern are grown, and all surfaces are turned to monocrystal. However, the crystal layers formed by this technique contain many crystal defects and could not be utilized for SOI devices.
In the meantime, the zone melt method as shown in FIG. 13 has been developed. In this method, the same wafer 1301 as in FIG. 12 is placed on the stage 1302 and heated. By energizing and scanning with long carbon heater 1303, a linear melted region 1304 is formed on wafer surface to produce monocrystal thin film. By this method, however, good crystal cannot be obtained because of the contamination of carbon from the carbon heater 1303. The wafer may be warped by heat or Si thin film may be cracked, and the method was not practically used. The temperature of wafer is partially increased to more than the melting point (1412.degree. C.) of silicon and this method cannot be applied for 3-dimensional IC. The devices built up on base material may be melted by heat during monocrystallization of the upper silicon layer, or the extreme deterioration of the characteristics may occur
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Ohmi Tadahiro
Shibata Tadashi
Umeda Masaru
Chaudhuri Olik
Ohmi Tadahiro
Tsai H. Jey
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