Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
2001-08-06
2002-07-23
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S323000, C438S330000, C438S342000
Reexamination Certificate
active
06423603
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a transistor structure that may be arranged in an array of transistors. In particular, the present invention relates to a transistor structure that may be included in a transistor array for low noise and high power applications.
BACKGROUND OF THE INVENTION
The noise performance of bipolar devices is mainly affected by base resistance. Base resistance chiefly includes two parts. The first part of the base resistance is resistance associated with an extrinsic base region. The second type of resistance included in base resistance is resistance associated with an intrinsic, or pinched-base, region.
In modern double polysilicon self-aligned silicided base bipolar transistors, the total base resistance consists primarily of the pinched-base resistance. This is a result of the relatively low resistivity of the silicided polysilicon extrinsic base region.
The power handling capability of a bipolar device may be limited by several factors. In some applications, the ability of a device's emitter to handle a large current density may be important to creating an effective power device. In considering a device that can handle a relatively large emitter current density and still maintain peak frequency performance, one problem lies in providing a desired current to the emitter without current crowding or heating effects degrading device performance.
For a transistor with a rectangular emitter, it has been recognized that for a given emitter width, or narrowest dimension, the pinched-base resistance is minimum for a geometry that minimizes the perimeter to area ratio. The lowest perimeter to area ratio is achieved with a square emitter geometry, that is, with width equal to length. It is also known that, in order to achieve the most uniform current distribution in the emitter-base region, the smallest possible emitter dimensions are desired. In general, a small emitter also has the advantage of achieving the highest frequency performance.
Known approaches to implementing a low-noise and/or high power double polysilicon transistor is to provide long narrow emitter fingers interspersed with base contacts on either side. The low-noise advantage of providing a long narrow emitter finger is to reduce the pinched-base resistance by keeping the intrinsic base resistance essentially in a parallel configuration, along the length of the emitter. For a power device, a long narrow emitter finger provides the desired, large emitter area, and, thus, emitter current, while keeping the emitter narrow to maintain high frequency performance.
One problem with the prior art approach of using a collection of long, narrow emitter fingers is that the base resistance achieved is not minimum because the perimeter to area ratio is not minimized. Another problem is that, for a power device, current crowding and heating along the length of the emitter are problematic. Additionally, for a power device, electromigration becomes more of a concern as the emitter fingers get longer.
In a power device with many long emitter fingers, second breakdown is a major concern. Second breakdown occurs when a particular emitter finger becomes hotter than the other emitter fingers. The hotter finger begins to demand more current due to a lowered base-emitter voltage (Vbe), as a result of the increased temperature. As more current flows into the emitter finger, it becomes even hotter. Eventually the finger will go into thermal runaway and fail.
In order to control this effect, a small resistance, or emitter ballast resistor, is typically put in series with each emitter finger to provide negative feedback. This negative feedback tends to prevent thermal runaway and allows all emitter fingers to conduct an equal share of the device current. It is, however, wasteful of valuable chip space to provide a large number of emitter ballast resistors for a power device with many emitter fingers.
Therefore, a low-noise transistor needs a minimum pinched-base resistance, which is achievable with an emitter having a low perimeter to area ratio. Also desirable for either a low-noise or high-power device is to keep the emitter dimensions small in order to maximize frequency performance. For a power device, a maximum area is desired along with some means of providing an emitter ballasting function for each emitter. Power devices are also constrained by electromigration of interconnect concerns in long emitter fingers.
SUMMARY OF THE INVENTION
In providing solutions to any one or more of the above problems as well as others, aspects of the present invention provide a transistor array including a plurality of transistors. Each transistor in the array includes an emitter region. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor in the array. A plurality of the base contacts are provided common to at least two transistors in the array. The array includes at least one collector reach through, or sinker, associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.
Other aspects of the present invention provide a method of forming a transistor array including a plurality of transistors. The method includes providing a substrate upon which is formed a buried layer subcollector region. A plurality of collector pedestals is provided in the buried layer subcollector region. At least one base region is provided on the collector pedestals. The base region includes an intrinsic semiconductor base region overlying each collector pedestal, and a silicided base region common to a plurality of the transistors. An emitter region is provided overlying each intrinsic base region. An emitter contact region is provided overlying each emitter region. At least one collector reach through is provided associated with each transistor. A collector reach through contact is provided overlying each collector reach through. At least one base contact is provided overlying the silicided base region and associated with each transistor, such that a plurality of the base contacts are common to at least two transistors in the array.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
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Groves Robert A.
Jadus Dale K.
Nguyen-Ngoc Dominique L.
Walter Keith M.
Abate Joseph P.
Connoly Bove Lodge & Hutz
International Business Machines - Corporation
Nguyen Tuan H.
LandOfFree
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