Method of forming a low loss FET

Details Method of forming a low loss FET Method of forming a low loss FET

1988-09-30

1989-10-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437150, 437193, 357234, 357 59, H01L 2122

Patent

active

048777498

ABSTRACT:
An improved FET is described in which a conductive layer connects the source structure to a truncated source extension which underlies an insulative gate layer and connects to a channel region. The conductive layer is of substantially lower resistivity than the source extension, thereby significantly reducing the lateral resistance of the device to diminish losses and reduce the likelihood of a parasitic bipolar transistor turning on. The invention can be implemented in both vertical and lateral devices. For a lateral device the drain is connected by a low resistance conductive layer to the gate region in a manner similar to the source.

REFERENCES:
patent: 4373251 (1983-02-01), Wilting
patent: 4419811 (1983-12-01), Rice
patent: 4503598 (1985-03-01), Vora et al.
patent: 4561168 (1985-12-01), Pitzer et al.
patent: 4616401 (1986-10-01), Takeuchi
patent: 4625388 (1986-12-01), Rice
Silicon Processing for the VLSI ERA by S. Wolf and Tauber, 1986, pp. 397-399.

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