Method of forming a level silicon oxide layer on two regions...

Details Method of forming a level silicon oxide layer on two regions... Method of forming a level silicon oxide layer on two regions...

1999-11-01

2001-05-22

Bowers, Charles (Department: 2813)

Coating processes

Direct application of electrical, magnetic, wave, or...

Pretreatment of substrate or post-treatment of coated substrate

C427S532000, C438S619000, C438S620000, C438S758000, C438S761000, C438S762000, C438S786000, C438S787000, C438S791000, C257S758000

Reexamination Certificate

active

06235354

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a level silicon oxide layer on a semiconductor wafer, and more particularly, to a method of forming a level silicon oxide layer on two regions of different heights on a semiconductor wafer.
2. Description of the Prior Art
In the semiconductor process, the silicon oxide (SiO
x
) manufacturing technique is very mature and the costs are very low. Hence, the silicon oxide layer is the most common material used as the dielectric layer for electrical isolation on a semiconductor wafer. The method of forming a dielectric layer made of silicon oxide utilizes the film deposition process which includes injecting silane (SiH
4
), tetra-ethyl-ortho-silicate (TEOS) and oxygen (O
2
). A dielectric film is created on the semiconductor wafer from the chemical reaction of the gas mixture.
Please refer to FIG.
1
.
FIG. 1
is a schematic diagram of depositing a silicon oxide layer
14
on a semiconductor wafer
10
. The prior art method of forming a level silicon oxide layer utilizes atmospheric pressure chemical vapor deposition (APCVD), which comprises putting the semiconductor wafer
10
on an APCVD machine (not shown) to perform the APCVD process, and then forming O
3
-TEOS by injecting reactive gasses comprising O
3
and TEOS to form the silicon oxide layer
14
on the semiconductor wafer
10
. The silicon oxide layer
14
thus formed by this method has a good gap filling ability so it has often been used as the inter-metal layer (IMD) or inter-layer dielectric (ILD).
Note that the surface of the semiconductor wafer
10
has many devices with different heights and made of different materials. For example, the substrate
12
made of silicon and the shallow trench
13
made of silicon dioxide form the lower surface. The anti-reflection layer (not shown) made of SiON and the mask
15
made of Si
x
N
y
form the higher surface. In
FIG. 1
, the region
16
means the lower region on the semiconductor wafer
10
is designated as the first region and labelled as region
16
, and the higher region on the semiconductor wafer
10
is designated as the second region and labelled as region
18
. The subsequent silicon oxide layer
14
will follow the lower and higher topography when it is deposited on to the semiconductor wafer
10
. Besides, the deposition rate of the O
3
-TEOS on the semiconductor wafer
10
changes with the material of the surface where the O
3
-TEOS is deposited onto. Ozone (O
3
) has an especially strong sensitivity to different surface materials. The order of the deposition rates for different material is as follows: silicon>silicon oxide formed by using thermal oxidation>silicon oxide formed by using deposition>Si
x
N
y
. When ozone is used to create a deposition layer, a silicon oxide layer
14
is formed with non-uniform height on the semiconductor wafer
10
.
Please refer to FIG.
2
.
FIG. 2
is a schematic diagram of the silicon oxide layer
14
shown in
FIG. 1
after polishing. For the stability of the subsequent semiconductor processes, after the deposition of the silicon oxide layer
14
as the IMD or ILD, a planarization process must be performed to level the surface of the semiconductor wafer
10
. During the planarization process, a spin-on glass (SOG) process is performed to form a SOG (not shown) on the silicon oxide layer
14
which has a non-uniform height on the semiconductor wafer
10
. Then, an etching back process or a chemical mechanical polishing (CMP) is performed to level the surface of the silicon oxide layer
14
. Planarization of silicon oxide layer
14
can also be performed directly with CMP. The prior art method of forming the level silicon oxide layer
14
on the semiconductor wafer
10
requiring performing the planarization process after the deposition process increases the complexity of the whole process and raises production costs.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a level silicon oxide layer on a semiconductor wafer to solve the above mentioned problem.
In a preferred embodiment, the present invention relates to a method of forming a level silicon oxide layer on a semiconductor wafer, the semiconductor wafer comprising a substrate having a first region containing no silicon nitride on its surface and a second region that is higher than the first region and which contains a silicon nitride layer on its surface. The deposition rate of forming a silicon oxide layer on the first region will be higher than that of the second region, the method comprising:
performing a cleaning process on the semiconductor wafer with an alkaline solution to uniform the deposition rate over the surface of the first region; and
performing a deposition process employing ozone as a reactive gas with a flow capacity of 80-200 g/L to form a silicon oxide layer above the first and second regions wherein the deposition rate of the silicon oxide layer on the first region is higher than that on the second region and the silicon oxide layer above the first region is leveled with that above the second region after a predetermined period of time.
It is an advantage of the present invention that the silicon oxide layer does not need any subsequent planarization process, and hence the production costs are reduced.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5849643 (1998-12-01), Gilmer et al.

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