Method of forming a high density self-aligned stack in trench

Details Method of forming a high density self-aligned stack in trench Method of forming a high density self-aligned stack in trench

1994-06-22

1995-07-04

Fourson, George

Fishing, trapping, and vermin destroying

437 47, 437 60, 437919, H01L 2170, H01L 2700

Patent

active

054299780

ABSTRACT:
A method, and resultant structure, is described for fabricating a high density DRAM cell in which a stacked capacitor using a pillar structure is formed in a trench. The DRAM cell includes a field effect transistor having a gate electrode and source/drain elements. A first insulating layer is patterned to create an exposed region wherein a first trench is formed in the silicon substrate, between the gate electrode and the field oxide. A second insulating layer is formed, and then removed from a portion of the bottom of the first trench to expose the silicon substrate. The silicon substrate is thermally oxidized at the bottom of the first trench to form an insulating layer mask. The remainder of the second insulating layer is removed. The portion of the silicon substrate in the first trench that is not masked by the insulating layer mask is vertically etched, whereby a pillar is formed under the insulating layer mask in the center of the final trench. The insulating layer mask is removed. A conductive layer is formed along the surfaces of the final trench and the pillar, adjacent to the source region of the field effect transistor, whereby the conductive layer is a capacitor signal node. A capacitor dielectric is formed over the conductive layer. A capacitor ground plate is formed over the capacitor dielectric.

REFERENCES:
patent: 4650544 (1987-03-01), Erb et al.
patent: 4859622 (1989-08-01), Eguehi
patent: 4978634 (1990-12-01), Shen et al.
patent: 4980310 (1990-12-01), Matsuda et al.
patent: 5106774 (1992-04-01), Hieda et al.
patent: 5143860 (1992-09-01), Mitchell et al.
patent: 5204280 (1993-04-01), Dhong et al.
patent: 5256588 (1993-10-01), Witek et al.
patent: 5317177 (1994-05-01), Nagata et al.
"A Novel Cell Structure Suitable For A 3 Volt Operation, Sector Erase Flash Memory", IEDM 92-599-602, Apr. 1992.
"A 0.6 .mu.m.sup.2 256Mb Trench DRAM Cell With Self-Aligned Buried Strap (BEST)" by L. Nesbit et al, pp. 627-630, Tech. Dig. of IEDM, 1993.

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