Semiconductor device manufacturing: process – Gettering of substrate – By layers which are coated – contacted – or diffused
Patent
1997-10-06
1999-11-30
Booth, Richard
Semiconductor device manufacturing: process
Gettering of substrate
By layers which are coated, contacted, or diffused
438637, 438675, 438686, 438687, 438688, 438632, 438646, H01L 21225, H01L 21385
Patent
active
059942061
ABSTRACT:
A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole on tope of the high conductivity metal. The via structure further includes a via plug material covering the high conductivity metal and substantially filling the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the via hole. Accordingly, by providing a via plug material within the via hole, the via plug material getters or dissolves the high conductivity metal that reaches the sidewalls of the dielectric layer during the via etch and sputter etch processes and the junction poisoning problems associated therewith are substantially minimized.
REFERENCES:
patent: 5016081 (1991-05-01), Brown et al.
patent: 5305519 (1994-04-01), Yamamoto et al.
patent: 5356836 (1994-10-01), Chen et al.
patent: 5454885 (1995-10-01), Dudoff et al.
patent: 5478758 (1995-12-01), Easter
patent: 5591673 (1997-01-01), Chao et al.
patent: 5637534 (1997-06-01), Takeyasu et al.
patent: 5668064 (1997-09-01), Park et al.
patent: 5698891 (1997-12-01), Tomita et al.
Chen Susan Hsuching
Gupta Subhash
Advanced Micro Devices , Inc.
Booth Richard
Nguyen Ha Tran
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