Method of forming a groove-like area in a semiconductor device

Details Method of forming a groove-like area in a semiconductor device Method of forming a groove-like area in a semiconductor device

1999-04-01

2003-04-15

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S524000

Reexamination Certificate

active

06548371

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and in particular, it relates to a semiconductor device in which element isolation is achieved by an oxide film and a method for manufacturing the semiconductor device.
2. Description of the Related Art
While the degree to which integration is achieved improves as semiconductor elements become smaller, element isolation must be considered as one of the factors that determine the degree of integration. The element isolation is an essential step performed in the semiconductor manufacturing process, and typical technologies adopted in the element isolation include the LOCOS focal oxidation of silicon) method and the trench method. In the LOCOS method, a thermally oxidized film formed by selectively oxidizing a semiconductor substrate is used as an element isolation area.
The trench isolation structure achieved through the trench method has been in use as a basic isolation structure for more than 10 years in the area of high speed bipolar type LSI devices. In addition, in recent years, STI (shallow trench isolation), which is a type of trench method, has been employed in the CMOS (complimentary metal-oxide semiconductor) logic and memory. STI, which prevents the formation of bird's beak present in the LOCOS structure in the prior art, eliminates superfluous conversion difference. As a result, advantages such as a great improvement in the degree to which elements can be integrated are achieved.
An example of the trench isolation structure in the prior art is now explained in reference to FIG.
9
.
First, an exposed front portion of a surface of an element substrate
801
constituted of silicon is thermally oxidized to approximately 3000 angstrom to form a thermally oxidized film
802
as illustrated in FIG.
9
(A). Next, a resist pattern is formed through regular photolithography technology and then, by using this resist pattern as a mask, the thermally oxidized film
802
is patterned as illustrated in FIG.
9
(B).
Then, after removing the resist pattern, opening portions are anisotropically etched using the thermally oxidized film
802
as a mask to form a trench
801
a
as illustrated in FIG.
9
(C). Next, by thermally oxidizing the side walls of the trench
801
a
to approximately 500 angstrom, a thermally oxidized film
803
is formed as illustrated in FIG.
9
(D). In the next step, the trench is completely embedded, as illustrated in FIG.
9
(E) by depositing a film
804
achieving outstanding coverage, which may be constituted of a low pressure CVD (LFCVD: low pressure chemical-vapor deposition) film over the entire surface of the substrate.
Then, if it is necessary to achieve global planarization due to varying gap intervals, as in the case when STI is adopted, planarization is implemented through CMP (chemical mechanical polishing). If, on the other hand, there are only narrow constant gap intervals present, the oxide film is etched back and flattened through dry etching of the oxide film to complete the isolation process, as illustrated in FIG.
9
(F).
Through the process described above, a full-depth trench isolation structure with hardly any conversion difference is formed. As a result, it becomes possible to achieve higher integration in a single layer and to reduce the parasitic capacity of the elements, the wiring capacity and the like, to result in a great advantage in realizing higher speed.
It is to be noted that trench structures such as STI differ from the structure employed in high speed bipolar devices in that the edges of the trenches are formed in extreme proximity to active areas. Because of this, the trench structure and the process for forming the trench greatly affects the characteristics of the active elements. What affects the characteristics of the active elements to the greatest degree is stress attributable to the trench structure and the formation process, and it presents a significant obstacle to the production of elements. The causes of such stress are primarily divided into stress factors attributable to the material characteristics of, mainly, the trench filler material, and stress factors occurring when oxidizing the right angle edges at the upper end of the trench that are seen when viewing the trench from the sectional direction.
The shape of the oxide film resulting from the concentrated stress occurring when thermally oxidizing the vicinity of the edges of a trench is explained in reference to FIG.
10
. When the thermally oxidized film
802
is formed by thermally oxidizing the element substrate
801
in which the trench has been formed at 1000 centigrade, the thickness of the oxide film is locally reduced in the vicinity of the edge
802
a
of the trench due to the concentration of stress occurring during the thermal oxidization resulting in the corner of the element substrate becoming even sharper. Such concentration of stress may result in an increase in the leak current of an MOS transistor formed in the vicinity or a crystal defect such as dislocation occurring during a subsequent heat treatment. Since they are caused by the corner of the element substrate being a sharp angle, it is necessary to improve upon its shape.
SUMMARY OF THE INVENTION
An object of the present invention, which has been completed by addressing the problems of the semiconductor devices in the prior art discussed above, is to provide a new and improved semiconductor device in which the shape of the element substrate that is affected by the thermal oxidation is improved to reduce the degree to which stress concentrates at the element substrate and a method for manufacturing this semiconductor device.
In order to achieve the object described above, in a first aspect of the present invention, a semiconductor device adopting a structure in which one active area formed on an element substrate is electrically isolated from another active area, that is characterized in that a groove-like area is formed between the one active area and the other active area with the groove-like area constituted of a side wall extending roughly vertical to the front surface of the element substrate and an inclined surface formed in the vicinity of the upper portion of the side wall at an angle larger than 90 degrees relative to the side wall, is provided.
In order to sent the angle formed by the side wall and the inclined surface larger than 90 degrees, the side wall may be, for instance, a surface {
111
} of the element substrate.
In this structure, the shape of the corner portion formed at the upper end of the trench is widened so that the angle formed by the side wall and the surface {
111
} is approximately 144.7 degrees, resulting in a great reduction in the concentration of stress at the corner portion occurring during the thermal oxidation. As a result, a reduction in the leak current is achieved and any crystal defects can be prevented, to achieve a great improvement in yield.
In addition, in a second aspect of the present invention, a method for manufacturing a semiconductor device adopting a structure in which one active area formed on an element substrate is electrically isolated from another active area, that includes a first step in which a groove-like area is formed at the element substrate through a treatment performed on the area between the one active area and the other active area under conditions whereby the etching rate on the surface {
100
} is higher than the etching rate on the surface {
111
} and a second step in which the bottom surface of the groove-like area is etched through anisotropic etching, is provided.
It is to be noted that the first step may be implemented under conditions whereby the etching rate on the surface {
100
} is essentially double or more than double the etching rate on the surface {
111
}, e.g., within a hydrogen gas atmosphere containing hydrogen chloride gas at a temperature of 800 centigrade or lower.
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