Method of forming a gate pattern in a semiconductor device

Details Method of forming a gate pattern in a semiconductor device Method of forming a gate pattern in a semiconductor device

2007-11-13

2007-11-13

Coleman, David W. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Mesa structure

C438S737000

Reexamination Certificate

active

11292764

ABSTRACT:
A gate pattern having a critical dimension after an etching process of 60-70nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a semiconductor wafer; forming a photoresist pattern by exposing and developing the ArF photoresist layer; etching the anti-reflection coating layer using the photoresist pattern as an etching mask; removing an oxide layer formed during etching of the anti-reflection coating layer; etching the gate electrode layer; and over-etching a remaining gate electrode layer.

REFERENCES:
patent: 6524964 (2003-02-01), Yu
patent: 2004/0009436 (2004-01-01), Lee et al.
patent: 2004/0127015 (2004-07-01), Lee
patent: 2004/0198065 (2004-10-01), Lee et al.
patent: 2004/0242014 (2004-12-01), Chakihara et al.
patent: 2006/0124587 (2006-06-01), Lee
patent: 2007/0049040 (2007-03-01), Bai et al.

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