Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2001-07-23
2003-09-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C118S695000
Reexamination Certificate
active
06617258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor
10
, as shown in
FIG. 1
, may be formed above a surface
15
of a semiconducting substrate or wafer
11
comprised of doped-silicon. The substrate
11
may be doped with either N-type or P-type dopant materials. The transistor
10
may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown).
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor
10
depicted in
FIG. 1
, are formed above a semiconducting substrate
11
. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in
FIG. 1
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is desirable in modern semiconductor processing that features be formed accurately due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width
12
that is approximately 0.18 &mgr;m (1800 Å), and further reductions are planned in the future. In general, the width
12
of the gate electrode
14
corresponds approximately to the channel length
13
of the transistor
10
when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, i.e., to form the gate electrode
14
to its desired critical dimension
12
.
Another factor that may affect transistor performance is the thickness of the gate insulation layer
16
. As stated above, there are constant efforts to increase the operating speed of transistor devices so as to improve the overall performance of integrated circuit devices made from such transistors. All other things being equal, the thinner the gate insulation layer
16
, the faster the transistor
10
will operate. Thus, there is a great desire to form very thin gate insulation layers
16
that are of acceptable quality. Typically, in current-generation transistors, the gate insulation layer
16
may have a thickness ranging from approximately 2-12 nm (20-120 Å), and further reductions are anticipated in the future as manufacturing technologies and/or materials improve.
The gate insulation layer
16
may be made from a variety of materials and by a variety of techniques. In many modern silicon-based transistors, the gate insulation layer
16
is comprised of a layer of silicon dioxide that is formed by an oxidation process in a furnace. In some applications, efforts have been made to form the gate insulation layer
16
by various deposition processes, e.g., chemical vapor deposition (“CVD”). However, semiconductor manufacturers continue to search for methods of manufacturing very thin, high-quality gate insulation layers
16
in a reliable manner that may be used in high volume production runs in a semiconductor manufacturing environment.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
In general, the present invention is directed to a method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and a system for accomplishing same. In one illustrative embodiment, the method comprises providing a substrate having a process layer formed thereabove, performing a wet etching process comprised of a duration parameter on the process layer to reduce a thickness of the process layer, and adjusting the duration parameter of the wet etching process if the reduced thickness of the process layer after the etching process is complete is not within acceptable limits.
In another illustrative embodiment, the present invention is directed to a system that is comprised of an etch tool for performing an etching process for a duration on a process layer formed above a semiconducting substrate to reduce a thickness of the process layer, and a controller for adjusting the duration of the etching process if the reduced thickness of the process layer after the etching process is performed is not within acceptable limits.
REFERENCES:
patent: 5776821 (1998-07-01), Haskell et al.
patent: 5801081 (1998-09-01), Warashina et al.
patent: 5920784 (1999-07-01), Lee
patent: 6245652 (2001-06-01), Gardner et al.
patent: 6258681 (2001-07-01), Fulford et al.
patent: 6409879 (2002-06-01), Toprac et al.
Ryskoski Matthew
Sonderman Thomas J.
Advanced Micro Devices , Inc.
Nelms David
Vu David
Williams Morgan & Amerson P.C.
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