Method of forming a field effect transistor

Details Method of forming a field effect transistor Method of forming a field effect transistor

1995-11-03

1997-11-18

Dutton, Brian

Fishing, trapping, and vermin destroying

437 45, H01L 21265

Patent

active

056887000

ABSTRACT:
A semiconductor processing method of forming a field effect transistor includes, a) providing a first layer of material over a substrate; b) providing a first opening through the first layer, the first opening having a width and a base; c) providing a second layer of material over the first layer and to within the first opening to a thickness which is less than one half the first opening width to less than completely fill the first opening and define a narrower second opening; d) anisotropically etching the second layer of material from outwardly of the first layer and from the first opening base to effectively provide inner sidewall spacers within the first opening; e) providing a gate dielectric layer within the second opening; f) providing a layer of electrically conductive gate material over the first layer and to within the second opening over the gate dielectric layer to fill the second opening with conductive gate material; g) without masking, planarize etching the conductive gate material layer substantially selective relative to the first layer to define a transistor gate within the second opening; and h) providing opposing source and drain regions relative to the transistor gate.

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J.Chung et al., "Deep-Submicrometer MOS Device Fabrication Using a Photoresist-Ashing Technique", IEEE Electron Device Letters, vol. 9, No. 4, Apr. 1988, pp. 186-188.
Shinichiro Kimura, et al., "A 0.1.mu.m-gate Elevated Source and Drain MOSFET fabricated by Phase-shifted Lithography", IEDM 91, pp. 13.8.1--13.8.3.
Tsukamoto, H., et al., "Sub 0.1.mu.m nMOSFET Utilizing Narrow Trench Gate and Selective Excimer Laser Annealing (SELA)", SSDM 1993, pp. 26-28.

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