Method of forming a ferroelectric memory device

Details Method of forming a ferroelectric memory device Method of forming a ferroelectric memory device

1999-12-22

2001-01-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S800000

Utility Patent

active

06168959

ABSTRACT:

BACKGROUND OF THE INVENTION
1
. Field of the Invention
The present invention relates to a method of forming a ferroelectric memory. In particular, the present invention relates to a method of forming a ferroelectric memory having improved method of connecting ferroelectric capacitors storing information and transistors controlling input/output of the information.
2. Description of the Prior Art
As a method of connecting capacitors and transistors in manufacturing a ferroelectric Random Access Memory (FeRAM), there is known a method of making storage node in the plugging way. This method, however, actually experiences many technical difficulties in manufacturing the ferroelectric memory device.
As another example, there is known a strapping method. Though this method is suitable for interconnection materials since it can make the depth of contact hole deeper. However, this method has also difficulties not capable of using metals having a low step coverage characteristic, and also in manufacturing a ferroelectric memory device having a desired electric characteristic since it requires only a good step coverage characteristic regardless of whether or not it is suitable as interconnection materials. Further, using this method, since the contact hole for interconnection is defined at the junction region of the transistor, it is difficult to obtain a sufficient capacity since the area enough to form the capacitor at the same position to the transistor is not secured. Thus, it has a difficulty in reducing the cell area per unit because it must form the capacitor at the field region portion.
In
FIG. 1
, there is shown a sectional view of a device for illustrating a conventional method of manufacturing a ferroelectric memory device.
Now, the method of manufacturing a conventional method of manufacturing a ferroelectric memory device will be below explained in detail by reference to FIG.
1
.
First, an underlying structure of a transistor consisting of a word line
13
, a junction region
14
etc., is formed on an active region of a semiconductor substrate
11
in which a device separation film
12
is formed. Next, a first interlayer insulating film
15
is formed on the entire structure. Then, the first interlayer insulating layer
15
is etched to expose the junction region
14
, thus forming a contact hole for bit line to form a bit line
16
. Thereafter, materials for a lower electrode, a ferroelectric material and materials for an upper electrode are sequentially formed on the entire structure. Next, they are patterned to form a capacitor
17
consisting of a lower electrode
17
A, a ferroelectric film
17
B and an upper electrode
17
C on the device separation region.
Next, a second interlayer insulating film
18
is formed on the entire structure and a contact hole is formed to expose the upper electrode
17
C of the capacitor
17
. Thereafter, the second interlayer insulating film
18
and the first interlayer insulating film
15
are sequentially etched to expose the junction region
14
. Then, after a metal layer is formed on it, it is patterned to form a local interconnection line that connects the junction region
14
and the upper electrode
17
C of the capacitor
17
.
However, if this method is used in manufacturing a ferroelectric memory device, a deep contact hole is formed, as a result of etching the second interlayer insulating film
18
and the first interlayer insulating film
15
so that the junction region
14
and the upper electrode
17
C of the capacitor
17
can be connected. Thus, it is extremely difficult to use a sputtering method by which the junction region
14
of the transistor and the upper electrode
17
C of the capacitor
17
are connected through this deep contact hole.
In addition, as it is difficult to form the transistor and the capacitor at the same position, there is limitation in reducing the cell area per unit.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the problems involved in the prior art, and to provide a method of manufacturing a ferroelectric memory device, which is capable of reducing the cell area per unit since the capacitor thereof can be positioned at the same position to the transistor and also of improving the device characteristic since it can use a metal suitable for interconnection materials but not used due to low step coverage.
In order to achieve the above object, the method of manufacturing a ferroelectric memory device according to the present invention comprises the steps of providing a semiconductor substrate in which a device separation film and a transistor are formed; forming a first interlayer insulating film on the entire structure and then forming a contact hole for bit lines and a contact hole for contact leading pad; forming and patterning a first conductive layer on the entire structure to form a bit line and a contact leading pad, respectively; forming a second interlayer insulating film on the entire structure including said bit line and said contact leading pad, sequentially forming materials for a lower electrode, ferroelectric materials and materials for upper electrode on the entire structure and then patterning it to form a capacitor consisting of the upper electrode, the ferroelectric film and the upper electrode; forming a third interlayer insulating film on the entire structure, and then etching a portion of said third interlayer insulating film on said capacitor and some portion of said third and second interlayer insulating films on said contact leading pad to form a contact hole for connecting the capacitor through which said upper electrode of said capacitor and the upper portion of said contact leading pad can be exposed; and forming a second conductive layer on the entire structure so that said contact hole for connecting said capacitor can be entirely buried, and then patterning it to forming a local interconnection line.


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