Method of forming a DRAM stacked capacitor cell

Details Method of forming a DRAM stacked capacitor cell Method of forming a DRAM stacked capacitor cell

1994-04-22

1995-05-09

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2700, H01L 2170

Patent

active

054139503

ABSTRACT:
A new stacked capacitor structure having increased capacitance and a method of fabrication was accomplished. The capacitor stores data in the form of stored charge and together with a field effect transistor (MOSFET) make up the individual Dynamic Random Access Memory (DRAM) storage cells on a DRAM chip. The improved capacitor is fabricated using an electrically conducting layer in the bottom electrode of the capacitor, which is substantially different in composition from silicon. The conducting layer preferably being a refractory metal or a refactory metal silicides, such as, tungsten (W) or tungsten silicide (WSi). The bottom electrode is formed from a multilayer composed of a thin polysilicon layer, the conducting layer and an upper thicker polysilicon layer. Vertical capacitor sidewalls are formed from the upper polysilicon layer by photoresist masking and then etching to the conducting layer. The conducting layer provides an etch end point for accurately etching to the correct depth without over etching. This provides a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom electrode and then forming the top capacitor electrode, thereby completing the stacked capacitor.

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"A Newly Designed Planar Stalked Capacitor Cell with High Dielectric Constant Film for 256Mbit DRAM", by T. Eimori et al, IEEE International Electronic Device Meeting Proceedings, Dec. 1993 pp. 631-634.

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