Method of forming a dram cell with a crown-fin-pillar structure

Details Method of forming a dram cell with a crown-fin-pillar structure Method of forming a dram cell with a crown-fin-pillar structure

1996-11-18

1998-12-22

Brown, Peter Toby

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438254, H01L 218242

Patent

active

058518975

ABSTRACT:
The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a crown shape capacitor with a plurality of horizontal fins. First, a first polysilicon layer is formed on a semiconductor substrate. A composition layer consists of BPSG and silicon oxide formed on a the first polysilicon layer. Then a contact hole is formed in the composition layer and the first polysilicon layer. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed in the contact hole and the composition layer. Then photolithgraphy and etching process is used to etch the second polysilicon layer, composition layer and first polysilicon layer. A third polysilicon layer is subsequently formed on the second polysilicon layer. An anisotropic etching is performed to etching the second and the third polysilicon layer. Then the composition layer is removed by BOE solution. A dielectric film is then formed along the surface of the first, second and third polysilicon layer. Finally, a forth polysilicon layer is formed on the dielectric film. Thus, a capacitor with a plurality of horizontal fins is formed.

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