Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2000-12-28
2002-05-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S462000, C438S940000
Reexamination Certificate
active
06383893
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, to semiconductor devices, such as a dynamic random access memory (DRAM) devices, wherein a plurality of such devices are fabricated on a wafer which is subsequently diced into individual chips.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces, forming devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC). the formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization. Such techniques are described in S. M. Sze,
VLSI Technology
, 2
nd
ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes.
To increase throughput, a plurality of ICs are fabricated on a wafer in parallel. The ICs are then separated into individual chips. The process of separating the wafer into individual chips is typically referred to as “dicing.” Conventionally, various dicing techniques, such as “grind-out” and “scribe and break” are employed. Such conventional dicing techniques are described in U.S. Pat. No. 3,942,508 to Shimizo, which is incorporated herein by reference for all purposes.
Refering to
FIG. 1
, a portion of a wafer
100
is depicted. Illustratively, the wafer comprises ICs
114
and
115
separated by a channel
120
. Channel
120
is the area in which the dicing tool cuts or scribes to separate the ICs. The width of the channel is, for example, about 100 microns (&mgr;m). Typically, the channel is covered with a dielectric layer
121
, such as oxide. The surface of the wafer is covered with hard and soft passivation layers
124
and
125
, respectively. The hard passivation layer, for example, comprises silicon dioxide or silicon nitride and the soft passivation layer comprises polyimide. The passivation layers serve to protect the surface of the ICs. Prior to wafer dicing, the passivation layers in the channel are typically removed, leaving a portion of the dielectric layer of the metallization.
As the dicing tool cuts or scribes the wafer, cracks and chips result. Due to the properties of the typical dielectric layer, cracks propagate from the area where the dicing tool cuts the wafer. Cracks in excess of a few microns in depth and several tenths of millimeters in length have been observed. In some instances, such cracks can extend from the cutting edge into the active chip areas, causing significant reliability degradation in the resulting ICs. This decreases the yield of ICs per wafer.
From the above discussion, it is apparent that there is a need to reduce the propagation of cracks and chips that result from dicing.
Other objects and advantages will become apparent from the following disclosure.
SUMMARY OF INVENTION
The invention provides a method for forming a crack stop structure and diffusion barrier in integrated circuits comprising the steps of:
providing a semiconductor wafer wherein said wafer contains at least one integrated circuit die finished through provision of BEOL structures;
forming a groove in the kerf region wherein the cross-section of said groove is substantially trapezoidal having a top width and a bottom width and wherein forming a groove comprises laser ablation; and
depositing a sealing layer. The sealing layer is chosen from materials that are substantially gas and moisture impermeant.
The present invention simplifies BEOL fabrication because it does not require special BEOL processing to create crack stop structures. BEOL fabrication is also simplified in that the present invention eliminates the requirement for first incorporating and then etching crack stop metals. The present invention also eliminates the additional processing steps and mask sets required.
The present invention provides for the removal of multiple layers of organic insulator and inorganic passivation layers using a single laser ablation process step. the invention provides for the passivation of exposed edges of the organic dielectric material in order to prevent the diffusion of oxygen and of moisture into the Cu features.
The invention provides semiconductor devices fabricated by the disclosed methods.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5691248 (1997-11-01), Cronin et al.
patent: 5872018 (1999-02-01), Lee
patent: 5898227 (1999-04-01), Geffken et al.
patent: 5925924 (1999-07-01), Cronin et al.
patent: 5977558 (1999-11-01), Lee
patent: 6066513 (2000-05-01), Pogge et al.
patent: 6084287 (2000-07-01), Mitwalsky et al.
patent: 6271578 (2000-08-01), Mitwalsky et al.
patent: 6180498 (2001-01-01), Geffken et al
patent: 6221775 (2001-04-01), Ference et al.
Begle Edward S.
Petrarca Kevin S.
Volant Richard P.
Connolly Bove & Lodge & Hutz LLP
Li Todd
Lindsay Walter L.
Niebling John F.
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