Method of forming a contact hole of a DRAM

Details Method of forming a contact hole of a DRAM Method of forming a contact hole of a DRAM

1999-06-01

2001-03-13

Utech, Benjamin (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S712000, C438S721000, C438S723000

Reexamination Certificate

active

06200904

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a DRAM, and more particularly to a method of forming a contact hole of a DRAM.
2. Description of the Prior Art
A DRAM is an element in semiconductor processing that is formed by a large number of single transistors and is a combination of DRAM memory cells. Each DRAM memory cell is formed by a metal oxide semiconductor (MOS) transistor connected in series to a capacitor. Each MOS transistor and capacitor is electrically connected by several word lines and bit lines to determine the address of every memory cell. The DRAM controls the opening and closing of the channel between the source and drain by controlling the voltage of the word line and generating “0” and “1” signals in the memory cell.
When the memory cell has a relatively high voltage a “1” signal is generated and the PN junction of the MOS transistor's drain on the substrate connected to the capacitor is unstable. In time, the capacitor will start to leak current. Therefore, the charge of the memory cell has to be refreshed cyclically if the voltage is to be maintained, otherwise current may leak causing the storage signal of “1” in the memory cell to fall to “0”.
Please refer to FIG.
1
.
FIG. 1
is a drawing of the structure of the memory cell
10
of a stack DRAM according to the prior art. A memory cell
10
of the DRAM is formed on a semiconductor wafer and comprises a Si substrate
12
, a MOS transistor
14
on the Si substrate, a dielectric layer
16
position on the Si substrate
12
and the MOS transistor
14
, two bit lines
18
within the dielectric layer
16
for transmitting information, a capacitor
20
for storing the charge and data, and a word line
22
for interconnecting the memory cells. The capacitor comprises an fieldplate
24
formed by doped poly-silicon as its upper layer, a storage node
26
as its lower layer and an interposed unit cell dielectric layer
28
with an oxide-nitride-oxide (ONO) structure between the field plate
24
and the storage node
26
.
In the formation of the memory cell
10
, the first step is to form the MOS transistor
14
, dielectric layer
16
and two bit lines
18
on the Si substrate
12
. Then, a contact hole
21
is formed within the dielectric layer
16
to be used as a node contact for the storage node
26
of the capacitor
20
. The contact hole
21
is formed vertically along the side walls of the two bit lines
18
while removing the dielectric layer
16
to the surface of the MOS transistor
14
. A silicon oxide layer
25
is then formed on the side walls of the two bit lines
18
followed by formation of a spacer
23
made of silicon nitride on the contact hole
21
. The spacer
23
serves as an electrical insulating layer between the storage node
26
and the bit line
18
and prevents electrical connection between the capacitor
20
and bit line
18
. This in turn prevents leakage of current. Lastly, the contact hole
21
is cleaned and the storage node
26
, the ONO dielectric layer
28
and the field plate
24
are formed. This completes the production of the capacitor
20
and memory cell
10
.
The cleaning solution used to clean the contact hole
21
may etch the exposed silicon oxide layer
25
in the contact hole
21
causing breakdown of the insulation between the storage node
26
and bit lines
18
. Further, the spacer
23
of the contact hole
21
is in direct contact with the drain on the Si substrate
12
. However, since the spacer
23
and the Si substrate
12
have different thermal expansion coefficients, thermal stress occurs in the contact region of the spacer
23
and the Si substrate
12
causing leakage of current in the PN junction on the Si substrate. This effect reduces the capability of storage charge of the capacitor
20
and increases the refresh frequency of the signal of the memory cell
10
so as to reduce the performance of the stack DRAM.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provides a method of forming a contact hole of a DRAM to solve the above mentioned problem.
In a preferred embodiment, the present invention relates to a method of forming a contact hole of a DRAM, the DRAM being formed in a semiconductor wafer and comprising:
a substrate;
a first dielectric layer positioned on the substrate;
two bit lines positioned on the first dielectric layer each having a rectangular-shaped cross section;
a second dielectric layer positioned on the first dielectric layer and two bit lines; and
a photo-resist layer positioned on the second dielectric layer, the photo-resist layer comprising an opening positioned above the space between the two bit lines and partially overlapping the two bit lines;
wherein the method of forming the contact hole comprises:
performing a first anisotropic etching process to vertically remove the second dielectric layer under the opening down to the top ends of two bit lines, and then continuing the process along the side walls of the two bit lines to vertically remove the second dielectric layer positioned between the two bit lines and the first dielectric layer in a downward direction to grossly form the contact hole while retaining a predetermined thickness of the first dielectric layer on the substrate;
performing a second anisotropic etching process to vertically remove the portions of the two bit lines under the opening down to the first dielectric layer;
removing the photo-resist layer in its entirety;
performing a thermal oxidation to form an insulating layer on the side walls of the two bit lines in the contact hole;
forming a passivation layer on the second dielectric layer and the surface of the contact hole to protect the insulating layer on the side wall of the two bit lines in the contact hole; and
performing a third etching process on the surface of the second dielectric layer and contact hole to remove the passivation layer and the remaining first dielectric layer from the bottom of the contact hole down to the substrate to complete the contact hole.
It is an advantage of the present invention that etching of the silicon oxide layer by the cleaning solution is prevented and the problem of thermal stress on the spacer is eliminated. This ensures proper insulation between the bit line and the contact hole of the capacitor.
Those and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5204286 (1993-04-01), Doan
patent: 5627095 (1997-05-01), Koh et al.
patent: 5763306 (1998-06-01), Tsai
patent: 5770510 (1998-06-01), Lin et al.
patent: 6025247 (2000-02-01), Chang et al.
patent: 6037216 (2000-03-01), Liu et al.

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