Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-03-03
2002-01-22
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S427000, C438S449000
Reexamination Certificate
active
06340624
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming a circuitry isolation regions within semiconductive wafer.
BACKGROUND OF THE INVENTION
Integrated circuitry is typically fabricated on and within semiconductor substrates, such a bulk monocrystalline silicon wafers. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Electrical components fabricated on substrates, and particularly bulk semiconductor wafers, are isolated from adjacent devices by insulating materials, such as insulating oxides. One isolation technique comprises trench isolation, whereby trenches are cut into a substrate and are subsequently filled with insulating oxide. Typical prior art problems associated with such isolation is described with reference to
FIGS. 1-3
.
Referring first to
FIG. 1
, a semiconductor wafer fragment
10
is comprised of a bulk monocrystalline silicon wafer having light background p-type doping of, for example, an average concentration of 1×10
13
ions/cm
3
. A pad oxide layer
14
has been formed over wafer
12
, and an oxidation masking layer
16
(typically Si
3
N
4
) is formed thereover. Layers
16
and
14
have been patterned as shown whereby the illustrated masking blocks overlie desired active area regions of the semiconductor wafer, and the exposed areas proximate thereto will constitute isolation regions to be formed.
Referring to
FIG. 2
, wafer fragment
10
is subject to a conventional dry etch chemistry, with or without plasma, which is principally fluorine-based, utilizing example components of one or more of CHF
3
, CF
4
and C
2
HF
5
. Such chemistry is selective to etch semiconductor wafer material
12
uniformly selective relative to masking layers
16
and
14
, and as well has a highly desired degree of anisotropy to produce the illustrated trenches
18
having substantially straight sidewalls
20
. Unfortunately, such etching also undesirably produces very sharp corners
22
at the lowestmost corners within trench
18
.
Referring to
FIG. 3
, wafer
10
has been subjected to suitable wet oxidation conditions to form oxide isolation regions
24
, with layers
16
and
14
having been subsequently removed. Unfortunately, the sharp corners
22
formed by the above or other etchings undesirably create high electric fields in these locations, and produce other adverse loading effects in the finished circuitry which is detrimental to circuit operation. Accordingly, it would be desirable to provide methods which enable production of trench recessed isolation material which do not require S sharp corners.
SUMMARY OF THE INVENTION
In accordance with but one aspect of the invention, a method of forming a circuitry isolation region within a semiconductive wafer comprises defining active area and isolation area over a semiconductive wafer. Semiconductive wafer material within the isolation area is wet etched using an etch chemistry which forms an isolation trench proximate the active area region having lowestmost corners within the trench which are rounded. Electrically insulating material is formed within the trench over the previously formed round corners. In accordance with another aspect, the semiconductive wafer material within the isolation area is etched using an etch chemistry which is substantially selective relative to semiconductive wafer material within the active area to form an isolation trench proximate the active area region.
In accordance with still another aspect, a method of forming a circuitry isolation region within a semiconductive wafer comprises masking an active area region over a semiconductive wafer. The active area region is provided with an impurity doping of a first conductivity type. An impurity of a second conductivity type is provided within the semiconductive wafer proximate the masked active area region. Second conductivity type provided semiconductive wafer material is substantially selectively etched relative to first conductivity type provided semiconductive wafer material forming a trench proximate the active area region. Electrically insulating material is formed within the trench.
REFERENCES:
patent: 4570325 (1986-02-01), Higuchi
patent: 4584055 (1986-04-01), Kayanuma et al.
patent: H204 (1987-02-01), Oh et al.
patent: 5118636 (1992-06-01), Hosaka
patent: 5668044 (1997-09-01), Ohno
patent: 5780353 (1998-07-01), Omid-Zohoor
patent: 5925811 (1999-07-01), Okabe et al.
patent: 5930650 (1999-07-01), Chung et al.
Doan Trung Tri
Durcan Mark
Micro)n Technology, Inc.
Pham Long
Wells, St. John, Roberts, Gregory & MAtkin, P.S.
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